RRAM cell and fabrication method therefor

A resistive random access memory (RRAM) cell implemented on a semiconductor substrate, the RRAM cell having a planar, horizontal architecture, comprising:

• two transistors disposed side-by-side on the semiconductor substrate, each having a gate, a source, and a drain;
• a dielectric layer formed on a surface of the semiconductor substrate, and a metal interconnection layer disposed in the dielectric layer;
• a plurality of resistive switching cells located on the dielectric layer, wherein the two transistors and the resistive switching cells are connected through the metal interconnection layer in the dielectric layer, electrodes of the resistive switching cells are connected in sequence to form a horizontal stack structure, and every two adjacent resistive switching cells within the plurality of resistive switching cells are divided into a resistive switching group so as to form multiple resistive switching groups, wherein a shared electrode node is located between every two adjacent resistive switching cells within each resistive switching group;
• gates of the two transistors are configured to apply different control signals respectively, sources of the two transistors are connected together and configured to apply a source signal jointly;
• drains of the two transistors are connected to the electrodes of the resistive switching cells at two ends of each resistive switching group respectively, and the shared electrode nodes of the multiple resistive switching groups are configured to apply different bit signals respectively.