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US 12,727,252 B2Granted
Microelectronic structure comprising logic device and passive device with thinner Si layer
AssigneeInternational Business Machines Corporation
InventorsRuilong Xie, Lawrence A. Clevenger, Kisik Choi, Terence Hook
Life of this patent
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Abstract
A microelectronic structure including a logic device and a passive device. The passive device includes a doped substrate, a silicide layer located on a backside surface of the doped substrate, and a metal plane located on a backside surface of the silicide layer.
Claims20
A microelectronic structure comprising:
- a logic device;
- and
- a passive device, wherein the passive device includes:
- a doped substrate;
- a plurality of source/drains;
- a silicide layer located on a backside surface of the doped substrate, wherein the silicide layer forms a uniform plane that extends laterally across the plurality of source/drains, wherein the silicide layer is in continuous contact with the backside surface of the doped substrate as it extends across the plurality of source/drains;
- a metal plane located on a backside surface of the silicide layer, wherein the metal plane forms a uniform plane that extends continuously across the surface of the silicide layer;
- and
- a backside interlayer dielectric layer located on the backside surface of the metal plane.
6 more elements
A microelectronic structure comprising:
- a logic device that includes a backside contact;
- and
- a passive device, wherein the passive device includes:
- a doped substrate;
- a plurality of source/drains;
- a silicide layer located on a backside surface of the doped substrate, wherein the silicide layer forms a uniform plane that extends laterally across the plurality of source/drains, wherein the silicide layer is in continuous contact with the backside surface of the doped substrate as it extends across the plurality of source/drains;
- a metal plane located on a backside surface of the silicide layer, wherein the metal plane forms a uniform plane that extends continuously across the surface of the silicide layer;
- and
- a backside interlayer dielectric layer located on the backside surface of the metal plane.
6 more elements
A method comprising:
- forming a logic device that includes a backside contact;
- and
- forming a passive device, wherein the passive device includes:
- a doped substrate;
- a plurality of source/drains;
- a silicide layer located on a backside surface of the doped substrate, wherein the silicide layer forms a uniform plane that extends laterally across the plurality of source/drains, wherein the silicide layer is in continuous contact with the backside surface of the doped substrate as it extends across the plurality of source/drains;
- a metal plane located on a backside surface of the silicide layer, wherein a combined height/depth of the doped substrate, the silicide layer, and the metal plane is in the range of about 30 to 80 nm, wherein the metal plane forms a uniform plane that extends continuously across the surface of the silicide layer;
- and
- a backside interlayer dielectric layer located on the backside surface of the metal plane.
6 more elements
Dependencies are inferred from the claim text.