Method of manufacturing a gate-all-around transistor using support cantilevers on opposing ends of a multilayered stack
AssigneeTokyo Electron Limited
InventorsH. Jim Fulford, Mark I. Gardner
Life of this patent
Estimating the term…
Loading patent…
AssigneeTokyo Electron Limited
InventorsH. Jim Fulford, Mark I. Gardner
Estimating the term…
A method of fabricating a semiconductor device includes forming on a patterned multilayered stack including sacrificial layers alternatingly stacked with channel layers on a substrate, the patterned multilayered stack having opposing sidewalls and opposing ends. Cantilever supports are formed on the substrate, each cantilever support being in contact with a respective opposing end of the patterned multilayered stack. A gate-all-around (GAA) structure is formed around each channel layer while the opposing ends of the multilayered stack are supported by the cantilever supports. The cantilever supports are removed from the opposing ends of the patterned multilayered stack to expose end portions of each channel layer, and source-drain (S-D) regions are formed on the exposed end portions of each respective channel layer.
A method of fabricating a semiconductor device, comprising:
A method of fabricating a gate-all-around (GAA) transistor, comprising:
Dependencies are inferred from the claim text.