Backside diffusion break
AssigneeInternational Business Machines Corporation
InventorsTsung-Sheng Kang, Sagarika Mukesh, Ruilong Xie, Alexander Reznicek
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Abstract
A semiconductor integrated circuit (IC) device includes a diffusion break region that has a diffusion break dielectric adjacent to or between diffusion break isolation wall(s). The diffusion break region may separate adjacent transistors. The diffusion break isolation wall(s) may include respective retained portions of a backside spacer, a bottom isolation, respective inner spacers, and residual active semiconductor nanolayers. The diffusion break region may be fabricated by depositing a diffusion break dielectric within a diffusion break opening against the diffusion break isolation wall(s).
Claims19
A semiconductor integrated circuit (IC) device comprising:
- a first diffusion break isolation wall comprising a first backside spacer, a first bottom isolation region directly upon the first backside spacer, a first alternating series of residual nanolayer channel layers and residual inner spacers directly upon the first bottom isolation region, and a first gate spacer directly upon the first alternating series of residual nanolayer channel layers and residual inner spacers;
- and
- a diffusion break dielectric directly against an outer sidewall of the first diffusion break isolation wall.
A semiconductor integrated circuit (IC) device comprising:
- a first diffusion break isolation wall comprising a first backside spacer, a first alternating series of residual nanolayer channel layers and residual inner spacers directly upon the backside spacer, and a first gate spacer directly upon the first alternating series of residual nanolayer channel layers and residual inner spacers;
- and
- a diffusion break dielectric directly against an outer sidewall of the first diffusion break isolation wall.
Dependencies are inferred from the claim text.