US 12,727,241 B2Granted

Stacked multi-gate device with diffusion stopping layer and manufacturing method thereof

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsChien-Yu Lin, Tien-Shun Chang, Yi-Syuan Siao, Su-Hao Liu, Chi On Chui

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Abstract

A method includes forming a fin structure including a first channel layer, a sacrificial layer, and a second channel layer over a substrate; forming a dummy gate structure across the fin structure; recessing the fin structure; epitaxially growing first source/drain epitaxial structures on opposite sides of the first channel layer; forming first dielectric layers to cover the first source/drain epitaxial structures, respectively; epitaxially growing second source/drain epitaxial structures on opposite sides of the second channel layer; removing the dummy gate structure and the sacrificial layer to form a gate trench between the first source/drain epitaxial structures and between the second source/drain epitaxial structures; and forming a metal gate structure in the gate trench. The second source/drain epitaxial structures are over the first dielectric layers, respectively.

Claims20

Dependent claims

A method comprising:

forming a fin structure over a substrate, wherein the fin structure comprises a first channel layer, a sacrificial layer over the first channel layer, and a second channel layer over the sacrificial layer;
forming a dummy gate structure across the fin structure;
recessing the fin structure by using the dummy gate structure as an etch mask;
after recessing the fin structure, epitaxially growing first source/drain epitaxial structures on opposite sides of the first channel layer;
forming first dielectric layers over the substrate and covering the first source/drain epitaxial structures, respectively;
performing a first implantation process to the first dielectric layers to form first doped dielectric layers over the first source/drain epitaxial structures, respectively;
forming second dielectric layers over the substrate and covering the first doped dielectric layers, respectively;
after forming the second dielectric layers, epitaxially growing second source/drain epitaxial structures on opposite sides of the second channel layer, wherein the second source/drain epitaxial structures are over the first dielectric layers, respectively;
removing the dummy gate structure and the sacrificial layer to form a gate trench between the first source/drain epitaxial structures and between the second source/drain epitaxial structures;
and
forming a metal gate structure in the gate trench.

8 more elements

A method comprising:

forming a fin structure over a substrate, wherein the fin structure comprises a bottom channel layer, a sacrificial layer, and a top channel layer arranged in a vertical direction;
forming a dummy gate structure over the fin structure;
removing portions of the fin structure not covered by the dummy gate structure;
forming first source/drain epitaxial structures on the substrate and connected to the bottom channel layer, wherein the first source/drain epitaxial structures comprise SiGe;
forming semiconductive isolation layers over the first source/drain epitaxial structures, respectively, wherein a germanium concentration of the semiconductive isolation layers is lower than a germanium concentration of the first source/drain epitaxial structures, and the semiconductive isolation layers comprise diffusion-blocking dopants, and each of the semiconductive isolation layers comprises:
a first epitaxial layer in contact with one of the first source/drain epitaxial structures;
and
a second epitaxial layer in contact with the first epitaxial layer, wherein the diffusion-blocking dopants are in at least one of the first epitaxial layer and the second epitaxial layer,
forming second source/drain epitaxial structures over the semiconductive isolation layers and connected to the top channel layer, wherein the second epitaxial layer of each of the semiconductive isolation layers is in contact with one of the second source/drain epitaxial structures;
and
replacing the dummy gate structure and the sacrificial layer with a metal gate structure.

8 more elements

A method comprising:

forming a first transistor over a substrate, wherein the first transistor comprises:
a first gate structure over the substrate;
a first channel layer embedded in the first gate structure;
first source/drain epitaxial structures on opposite sides of the first gate structure and connected to the first channel layer;
depositing a first bonding layer over the first transistor and the substrate;
bonding the first bonding layer with a second bonding layer to form a semiconductor stack over the first transistor through the first bonding layer and the second bonding layer;
after bonding the first bonding layer with the second bonding layer, patterning the semiconductor stack to form a fin structure over the second bonding layer;
forming a dummy gate structure across the fin structure;
recessing the fin structure by using the dummy gate structure as an etch mask to form recesses in the fin structure, wherein the recesses expose the second bonding layer;
after recessing the fin structure, performing an implantation process with dopants to the recesses, wherein the dopants comprise carbon, fluorine, xenon, silicon, nitrogen, oxygen, sulfur, or combinations thereof, and after performing the implantation process with the dopants, the dopants are doped in the second bonding layer;
after performing the implantation process, depositing second source/drain epitaxial structures in the recesses, respectively;
and
replacing the dummy gate structure with a second gate structure to form a second transistor over the first transistor.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/330,300Filed 6 Jun 2023
Published: US 2024/0413155 A112 Dec 2024
Granted: 1 Sep 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10D 84/856
Complementary IGFETs, e.g. CMOS: the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
H10D 30/014
Manufacture or treatment: of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron…
H10D 30/43
FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels: having one-dimensional [1D] charge…
H10D 30/6735
Characterised by the shapes, relative sizes or dispositions of the gate electrodes: having gates fully surrounding the channels, e.g. gate-all-around