Method of forming a nano-FET semiconductor device having a spacer with a reducer seam
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsLi-Chi Yu, Cheng-I Chu, Chen-Fong Tsai, Yi-Rui Chen, Sen-Hong Syue, Wen-Kai Lin, Yoh-Rong Liu, Huicheng Chang, Yee-Chia Yeo
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Abstract
Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.
Claims20
A device comprising:
- a first nanostructure;
- a second nanostructure over the first nanostructure;
- a source/drain region adjacent the first nanostructure;
- a gate structure surrounding the first nanostructure and the second nanostructure;
- and
- a first inner spacer between the first nanostructure and the second nanostructure, the first inner spacer being between the gate structure and the source/drain region, the first inner spacer having oxidation on a first side of the first inner spacer, the first side of the first inner spacer contacting the source/drain region, the first inner spacer having a seam, wherein the seam comprises a first surface of the first inner spacer that is cross-linked to a second surface of the first inner spacer, wherein the seam is a closed seam that comprises a plurality of small gaps, wherein the oxidation has a gradient of concentration which continuously decreases laterally deeper into the first inner spacer from the first side of the first inner spacer.
A transistor comprising:
- a first nanostructure over a semiconductor substrate, the first nanostructure including a first end;
- a second nanostructure over the first nanostructure, the second nanostructure including a second end;
- a spacer between the first end and the second end;
- a gate dielectric surrounding the first nanostructure and the second nanostructure, the gate dielectric having an interface with a first side of the spacer;
- and
- a source/drain region adjacent the first end and the second end, the source/drain region having an interface with a second side of the spacer, the second side of the spacer opposite the first side, wherein the first side of the spacer has a first dishing profile, wherein the second side of the spacer has a second dishing profile, wherein the second dishing profile is less dished than the first dishing profile, wherein the spacer includes a seam and a plurality of gaps along the seam, wherein a first oxidation concentration has a concentration gradient which continuously decreases from the second side of the spacer toward the first side of the spacer.
A transistor comprising:
- a first nanostructure over a semiconductor substrate, the first nanostructure including a first end;
- a second nanostructure over the first nanostructure, the second nanostructure including a second end;
- a spacer between the first end and the second end;
- a gate dielectric surrounding the first nanostructure and the second nanostructure, the gate dielectric having an interface with a first side of the spacer;
- and
- a source/drain region adjacent the first end and the second end, the source/drain region having an interface with a second side of the spacer, the second side of the spacer opposite the first side, wherein the first side of the spacer has a first dishing profile, wherein the second side of the spacer has a second dishing profile different than the first dishing profile, wherein the second side of the spacer has a higher oxygen content than the first side of the spacer, wherein the spacer includes a cross-linked seam and gaps along the cross-linked seam, wherein the higher oxygen content at the second side of the spacer continuously decreases in a gradient from the second side toward the first side.
Dependencies are inferred from the claim text.