Transistor gate structures and methods of forming the same

A method comprising:

• forming a gate dielectric layer around a first nanostructure and a second nanostructure;
• depositing a p-type work function tuning layer on the gate dielectric layer;
• depositing an aluminum oxide layer on the p-type work function tuning layer, wherein the aluminum oxide layer, the p-type work function tuning layer, and the gate dielectric layer conformally line an opening between the first nanostructure and the second nanostructure;
• annealing the aluminum oxide layer, the p-type work function tuning layer, and the gate dielectric layer;
• removing a portion of the aluminum oxide layer to expose a portion of the p-type work function tuning layer underlying the removed portion of the aluminum oxide layer;
• and
• depositing a fill layer on the exposed portion of the p-type work function tuning layer, the fill layer filling remaining portions of the opening between the first nanostructure and the second nanostructure.

A method comprising:

• forming a gate dielectric layer on a channel region of a semiconductor feature;
• depositing a work function tuning layer on the gate dielectric layer, the work function tuning layer comprising a first work function tuning element;
• depositing a capping layer on the work function tuning layer, the capping layer comprising a second work function tuning element, the second work function tuning element different from the first work function tuning element;
• driving the first work function tuning element and the second work function tuning element into the gate dielectric layer by performing an anneal process while the capping layer covers the work function tuning layer;
• after performing the anneal process, removing the capping layer;
• and
• depositing a fill layer on the work function tuning layer.