Semiconductor device with voltage resistant structure
AssigneeRohm Co., Ltd.
InventorsYuki Nakano, Ryota Nakamura
Life of this patent
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Abstract
A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.
Claims17
A semiconductor device including an MISFET (Metal Insulator Field Effect Transistor) comprising:
- a source pad, a gate pad and a gate finger;
- a semiconductor layer having a cell portion including a plurality of unit cells having a planar-gate type structure, an outer peripheral portion disposed around the cell portion, a base surface and a lower surface formed at a relatively low height position with respect to the base surface;
- a p-type well formed in a surface portion of the semiconductor layer in a manner extending across the cell portion and the outer peripheral portion;
- a well contact region formed in an inner region of the p-type well;
- a surface insulating film formed on a surface of the semiconductor layer in a manner extending across the cell portion and the outer peripheral portion;
- a gate electrode formed on the semiconductor layer via a gate insulating film, wherein
- the source pad is connected to the unit cell and the well contact region via a first contact hole in the surface insulating film, and
- the gate finger is electrically connected to the gate electrode via a second contact hole in the surface insulating film.
A semiconductor device including an MISFET (Metal Insulator Field Effect Transistor) comprising:
- a source pad, a gate pad and a gate finger;
- a semiconductor layer having a cell portion including a plurality of unit cells having a planar-gate type structure, an outer peripheral portion disposed around the cell portion, a base surface and a lower surface formed at a relatively low height position with respect to the base surface;
- a p-type well formed in a surface portion of the semiconductor layer in a manner extending across the cell portion and the outer peripheral portion;
- a well contact region formed in an inner region of the p-type well;
- a surface insulating film formed on a surface of the semiconductor layer in a manner extending across the cell portion and the outer peripheral portion;
- a gate electrode formed on the semiconductor layer via a gate insulating film, wherein
- the source pad is connected to the unit cell and the well contact region via a first contact hole in the surface insulating film,
- the gate finger is electrically connected to the gate electrode via a second contact hole in the surface insulating film,
- the unit cells in the cell portion are regularly arrayed in a polygonal shape in plan view,
- the semiconductor layer is made of SiC, and
- the semiconductor device further comprises a substrate, wherein the semiconductor layer includes an epitaxial layer formed by an epitaxial growth on a surface of the substrate and has a lower impurity concentration than the substrate.
Dependencies are inferred from the claim text.