US 12,727,204 B2 · Non-volatile memory device

Abstract

A non-volatile memory device includes at least one memory cell including a substrate, an assist gate, a byte select gate, a floating gate, and an upper gate. The substrate includes a first doped region and a second doped region. The assist gate is disposed on the substrate and adjacent to the second doped region. The byte select gate is disposed on the substrate and adjacent to the first doped region. The floating gate is disposed on the substrate and between the assist gate and byte select gate, and the floating gate includes an upper edge higher than top surfaces of the assist gate and the byte select gate. The upper gate covers the assist gate and the floating gate, and the upper gate is spaced apart from the byte select gate. The upper edge of the floating gate is embedded in the upper gate.

Claims17

Dependent claims

A non-volatile memory device, comprising at least one memory cell, wherein the at least one memory cell comprises:

a substrate comprising a first doped region and a second doped region;
an assist gate disposed on the substrate and adjacent to the second doped region;
a byte select gate disposed on the substrate and adjacent to the first doped region;
a floating gate disposed on the substrate and between the assist gate and byte select gate, wherein the floating gate comprises an upper edge higher than top surfaces of the assist gate and the byte select gate;
and
an upper gate covering the assist gate and the floating gate, wherein the upper gate is laterally spaced apart from the byte select gate, and the upper edge of the floating gate is embedded in the upper gate,
wherein the byte select gate is configured to turn on or turn off a channel region in the substrate under the byte select gate, and wherein the byte select gate is configured to be electrically connected to the upper gate.

4 more elements

A non-volatile memory device, comprising:

a row of memory cells arranged in a first byte region and second byte region respectively, wherein each memory cell comprises an assist transistor, a floating gate transistor, and a byte select transistor being connected in series;
a first erase gate line electrically connected to erase gates of the floating gate transistors in the first byte region;
a second erase gate line electrically connected to erase gates of the floating gate transistors in the second byte region, wherein the second erase gate line is configured to be biased independently of the first erase gate line;
a first select gate line electrically connected to select gates of the byte select transistors in the first byte region;
and
a second select gate line electrically connected to select gates of the byte select transistors in the second byte region, wherein the second select gate line is configured to be biased independently of the first select gate line,
wherein the erase gates of the floating gate transistors in the first byte region are electrically connected to the select gates of the byte select transistors in the first byte region.

4 more elements

Dependencies are inferred from the claim text.

Non-volatile memory device

Life of this patent

Non-volatile memory device

Life of this patent

Abstract

Claims17