HEMT transistor of the normally off type including a trench containing a gate region and forming at least one step, and corresponding manufacturing method

A method for manufacturing normally off heterostructure field-effect transistor (HEMT), the method comprising:

• forming a semiconductor heterostructure including:
• a first semiconductor layer;
• and
• a second semiconductor layer on the first semiconductor layer;
• forming a passivation layer of dielectric material on the semiconductor heterostructure;
• forming a trench extending entirely through the passivation layer, entirely through the second semiconductor layer, and partially through the first semiconductor layer, the trench including:
• a bottom surface;
• a first step on a first side of the trench, the first step having a planar horizontal surface and a planar vertical surface, the planar horizontal surface of the first step being higher in the trench than the bottom surface;
• a plurality of second steps on a second side of the trench each having a respective planar horizontal surface and a respective planar vertical surface, the planar horizontal surface of second steps each being higher in the trench than the bottom surface;
• forming, after forming the trench, a dielectric layer coating the first and second steps;
• forming, after forming the trench, a conductive gate region on the dielectric layer and filling the trench;
• and
• forming, after forming trench, a source metallization extending through the patterned passivation layer and in contact with the patterned second semiconductor layer.

A method for manufacturing normally off heterostructure field-effect transistor (HEMT), the method comprising:

• forming a semiconductor heterostructure including:
• a first semiconductor layer of gallium nitride;
• and
• a second semiconductor layer of aluminum gallium nitride;
• forming a passivation layer of dielectric material on the semiconductor heterostructure;
• forming a trench in the passivation layer and the semiconductor heterostructure, the trench including:
• a bottom surface;
• a planar vertical sidewall in the semiconductor heterostructure on a first side of the trench;
• and
• a plurality of first steps each including a respective planar horizontal surface higher in the trench than the bottom surface and a respective planar vertical surface laterally opposite the planar vertical sidewall on a second side of the trench in the semiconductor heterostructure, wherein the planar vertical sidewall extends entirely through the second semiconductor layer, wherein each respective planar horizontal surface is lower than a top surface of the semiconductor heterostructure.