Semiconductor package and method of manufacturing the same

A semiconductor package comprising:

• a first semiconductor chip;
• a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip;
• a front connection pad disposed on a lower surface of each of the plurality of second semiconductor chips;
• a rear connection pad attached on an upper surface of the first semiconductor chip and each of the plurality of second semiconductor chips;
• a chip connection terminal disposed between the front connection pad and the rear connection pad;
• an insulating adhesive layer disposed between the first semiconductor chip and a lowermost second semiconductor chip and between two adjacent second semiconductor chips of the plurality of second semiconductor chips, the insulating adhesive layer including a first material layer covering a sidewall of the chip connection terminal and a second material layer disposed on at least one side of the first material layer to have viscosity which is greater than viscosity of the first material layer;
• and
• a molding layer covering side surfaces of the first semiconductor chip and the plurality of second semiconductor chips and directly contacting a side surface of the second material layer,
• wherein a maximum height of the first material layer in a vertical direction is equal to a maximum height of the second material layer in the vertical direction.

A semiconductor package comprising:

• a redistribution layer (RDL) interposer;
• a buffer chip including a first substrate, a plurality of first through electrodes passing through at least a portion of the first substrate, a first wiring layer disposed on an active surface of the first substrate, the first wiring layer including a plurality of first wiring patterns, and a plurality of first wiring vias, a first inter-wiring insulation layer surrounding the plurality of first wiring patterns and the plurality of first wiring vias, the active surface of the first substrate facing the RDL interposer, and the buffer chip being attached on the RDL interposer;
• a plurality of memory cell chips each including a second substrate, a plurality of second through electrodes passing through at least a portion of the second substrate, a second wiring layer disposed on an active surface of the second substrate, the second wiring layer including a plurality of second wiring patterns, a plurality of second wiring vias, and a second inter-wiring insulation layer surrounding the plurality of second wiring patterns and the plurality of second wiring vias, the active surface of the second substrate facing the buffer chip, and the plurality of memory cell chips being sequentially stacked on the buffer chip;
• a plurality of front connection pads attached on a lower surface of the second wiring layer;
• a plurality of rear connection pads attached on an inactive surface of the first substrate and an inactive surface of the second substrate;
• a plurality of chip connection terminals disposed between the buffer chip and the plurality of memory cell chips and between the plurality of front connection pads and the plurality of rear connection pads;
• an insulating adhesive layer disposed between the buffer chip and the plurality of memory cell chips, the insulating adhesive layer including a first material layer covering a sidewall of a corresponding chip connection terminal and a second material layer disposed on at least one side of the first material layer to have viscosity which is greater than viscosity of the first material layer;
• and
• a molding layer surrounding the plurality of memory cell chips and the insulating adhesive layer, on the buffer chip,
• wherein a maximum height of the first material layer in a vertical direction is equal to a maximum height of the second material layer in the vertical direction.