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US 12,727,171 B2Granted
Three dimensional semiconductor device with memory stack
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChenchen Wang, Chun-Chieh Lu, Chi On Chui, Yu-Ming Lin, Sai-Hooi Yeong
Life of this patent
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Abstract
A device includes a first transistor over a substrate, a second transistor disposed over the first transistor, and a memory element disposed over the second transistor. The second transistor includes a channel layer, a gate dielectric layer surrounding a sidewall of the channel layer, and a gate electrode surrounding a sidewall of the gate dielectric layer.
Claims20
A method of manufacturing a semiconductor device, comprising:
- forming a first transistor at least partially within a substrate;
- forming a first conductive line over the first transistor;
- forming a second transistor over and vertically overlapping with the first transistor, by:
- forming a gate electrode layer over the first conductive line,
- patterning an opening in the gate electrode layer,
- forming a gate dielectric layer on a sidewall of the opening, and
- forming a channel layer on a sidewall of the gate dielectric layer in the openings,
- forming a memory element disposed over the channel layer;
- and
- patterning the gate electrode layer to define a gate electrode, wherein the gate electrode surrounds a sidewall of the channel layer.
7 more elements
A method of manufacturing a semiconductor device, comprising:
- forming a first transistor at least partially within a substrate, the substrate defining a horizontal plane;
- forming a first conductive line over the first transistor;
- forming over, aligned to, and vertically overlapping the first transistor, a vertically-extending column of channel region material surrounded by a ring-shaped gate dielectric, the ring-shaped gate dielectric being surrounded by a gate electrode, wherein the channel region material, the ring-shaped gate dielectric, and the gate electrode are configured to act as a select transistor for a memory cell, and wherein the first conductive line is configured to act as a source line for the select transistor;
- depositing a stack comprising a bottom electrode layer, a memory material layer, and a top electrode layer on the select transistor;
- patterning the stack to form the memory cell over, aligned to, and vertically overlapping the select transistor;
- and
- forming a second conductive line over the memory cell, the second conductive line being configured to act as a bit line for the memory cell.
4 more elements
A method of forming a semiconductor device, the method comprising:
- forming a plurality of transistors on a substrate, the substrate forming a horizontally extending plane;
- forming an interconnect structure over the plurality of transistors, the interconnect structure including a stack of conductive layers embedded within respective dielectric layer of a stack of dielectric layers;
- forming a memory cell between a first conductive layer of the stack of conductive layers and a second conductive layer of the stack of conductive layers by:
- forming a select transistor on the first conductive layer, the select transistor including a vertically extending channel region surrounded by a ring-shaped gate dielectric surrounded by a gate electrode;
- forming a memory cell on, aligned to, and vertically overlapping with the select transistor, the memory cell including a bottom electrode layer, a memory material layer, and a top electrode layer;
- and
- depositing the second conductive layer of the stack of conductive layers on and electrically connected to the memory cell.
4 more elements
Dependencies are inferred from the claim text.