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US 12,727,165 B1Granted
Etch stop layer based integration process for embedded memory
AssigneeKepler Computing Inc.
InventorsNoriyuki Sato, Debraj Guhabiswas, Tanay Gosavi, Niloy Mukherjee, Amrita Mathuriya, Sasikanth Manipatruni
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Abstract
An integration process including an etch stop layer for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.
Claims19
A device comprising:
- a first region comprising:
- a first conductive interconnect within a first level, the first conductive interconnect comprising a first lateral thickness;
- and
- a second level above the first level, the second level comprising:
- a memory device above the first conductive interconnect, the memory device comprising ferroelectric material or paraelectric material, wherein the memory device comprises a second lateral thickness;
- an electrode structure coupled between the memory device and the first conductive interconnect, the electrode structure comprising a third lateral thickness, wherein the first lateral thickness and the third lateral thickness are respectively less than the second lateral thickness;
- an etch stop layer comprising a dielectric material, the etch stop layer laterally surrounding the electrode structure;
- a spacer on a first sidewall of the memory device and above the electrode structure;
- a via electrode on the memory device, wherein the etch stop layer comprises:
- a first surface below the memory device;
- a second surface below the spacer, wherein the first surface and the second surface are at different levels;
- and
- a second sidewall connecting the first surface and the second surface, wherein the second sidewall is vertical, and wherein the spacer extends below the first surface;
- and
- a second region adjacent to the first region, the second region comprising an interconnect structure, the interconnect structure comprising:
- a second conductive interconnect within the first level;
- a metal line within the second level;
- and
- a via structure within the second level, the via structure coupling the metal line with the second conductive interconnect, wherein at least a first portion of the via structure is adjacent to the etch stop layer, and wherein the etch stop layer is on at least a portion of the second conductive interconnect.
16 more elements
A system comprising:
- a processor;
- a communication interface communicatively coupled to the processor;
- and
- a memory coupled to the processor, wherein the memory comprises:
- bit-cells, wherein one of the bit-cells includes:
- a first region comprising:
- a first conductive interconnect within a first level, the first conductive interconnect comprising a first lateral thickness;
- and
- a second level above the first level, the second level comprising:
- a memory device above the first conductive interconnect, the memory device comprising ferroelectric material or paraelectric material, wherein the memory device comprises a second lateral thickness;
- an electrode structure coupled between the memory device and the first conductive interconnect, the electrode structure comprising a third lateral thickness, wherein the first lateral thickness and the third lateral thickness are respectively less than the second lateral thickness;
- an etch stop layer comprising a dielectric material, the etch stop layer laterally surrounding the electrode structure;
- a spacer on a first sidewall of the memory device, wherein the etch stop layer comprises:
- a first surface below the memory device;
- a second surface below the spacer, wherein the first surface and the second surface are at different levels;
- and
- a second sidewall connecting the first surface and the second surface, wherein the second sidewall is vertical, and wherein the spacer extends below the first surface;
- and
- a via electrode on the memory device;
- and
- a second region adjacent to the first region, the second region comprising an interconnect structure, the interconnect structure comprising:
- a second conductive interconnect within the first level;
- a metal line within the second level;
- and
- a via structure within the second level, the via structure coupling the metal line with the second conductive interconnect, wherein at least a first portion of the via structure is adjacent to the etch stop layer, and wherein the etch stop layer is on at least a portion of the second conductive interconnect.
22 more elements
Dependencies are inferred from the claim text.