Non-volatile memory cell with ONO compound insulation layer between floating and control gates and a method of fabrication

A method, comprising:

• forming a first insulation layer on an upper surface of a semiconductor substrate;
• forming a first conductive layer on the first insulation layer;
• forming a second insulation layer on the first conductive layer;
• forming a trench that extends through the second insulation layer, the first conductive layer, the first insulation layer, and into the semiconductor substrate;
• filling the trench with fill insulation material;
• removing the second insulation layer and an upper portion of the fill insulation material;
• forming a compound insulation layer on the first conductive layer and on the fill insulation material in the trench, wherein the compound insulation layer comprises a nitride sublayer between a lower oxide sublayer and an upper oxide sublayer;
• removing portions of the upper oxide sublayer and the nitride sublayer disposed on the fill insulation material in the trench;
• and
• forming a second conductive layer on the compound insulation layer and on the lower oxide sublayer in the trench.

A semiconductor device, comprising:

• a semiconductor substrate comprising:
• an upper surface,
• alternating active regions and isolation regions that have lengths extending in a parallel manner in a first direction, and
• respective ones of the isolation regions include a trench formed into the upper surface, having a length extending in the first direction, and containing fill insulation material filling the trench;
• a first strip of conductive material having a length extending in a second direction orthogonal to the first direction and over the active regions and the isolation regions;
• a plurality of floating gates disposed over and insulated from the upper surface, wherein respective ones of the floating gates are:
• disposed in one of the active regions, between adjacent ones of the isolation regions,
• disposed under the first strip of conductive material, and
• insulated from the first strip of conductive material by a compound insulation layer, wherein the compound insulation layer comprises a nitride sublayer between a lower oxide sublayer and an upper oxide sublayer and wherein the nitride sublayer does not extend completely across the isolation regions;
• a second strip of conductive material having a length extending in the second direction over the active regions and the isolation regions;
• and
• a third strip of conductive material having a length extending in the second direction over the active regions and the isolation regions, wherein the first strip of conductive material is disposed between and insulated from the second strip of conductive material and the third strip of conductive material.