US 12,727,157 B2 · Memory cell including dual-antifuse device, memory structure, and operating method

Abstract

Disclosed is a memory cell including a dual-antifuse device between a first pass-gate transistor and a second pass-gate transistor. The dual-antifuse device includes first and second antifuses having a common terminal and each also having an additional terminal opposite the common terminal. The first pass-gate transistor is connected between a first bitline and the additional terminal of the first pass-gate transistor. The second pass-gate transistor is connected between a second bitline and the additional terminal of the second pass-gate transistor. The common terminal of the first and second antifuses and gates of the first and second pass-gate transistors are connected to a wordline. Also disclosed is a memory structure including an array of such memory cells and an associated operating method. Within the array, different wordline and bitline bias conditions can be employed in order to reliably perform programming or read operations of a selected antifuse in a selected cell.

Claims20

Dependent claims

A structure comprising:

a dual-antifuse device including a first antifuse and a second antifuse, wherein the first antifuse and the second antifuse have a common terminal connected to a wordline, wherein the first antifuse has a first additional terminal, and the second antifuse has a second additional terminal electrically isolated from the first additional terminal;
a first pass-gate transistor connected between a first bitline and the first additional terminal;
and
a second pass-gate transistor connected between the second additional terminal and a second bitline, wherein gates of the first pass-gate transistor and the second pass-gate transistor are connected to the wordline.

1 more element

A structure comprising:

an array of cells arranged in rows and columns;
wordlines for the rows;
and
first and second bitlines for the columns, wherein each cell includes:
a dual-antifuse device including a first antifuse and a second antifuse, wherein the first antifuse and the second antifuse have a common terminal connected to a wordline for a row, wherein the first antifuse has a first additional terminal, and the second antifuse has a second additional terminal electrically isolated from the first additional terminal;
a first pass-gate transistor connected between a first bitline for a column and the first additional terminal;
and
a second pass-gate transistor connected between the second additional terminal and a second bitline for the column, wherein gates of the first pass-gate transistor and the second pass-gate transistor are connected to the wordline.

5 more elements

A method comprising:

providing a structure, wherein the structure includes
an array of cells arranged in rows and columns;
wordlines for the rows;
and
first and second bitlines for the columns, wherein each cell includes:
a dual-antifuse device including a first antifuse and a second antifuse, wherein the first antifuse and the second antifuse have a common terminal connected to a wordline for a row, wherein the first antifuse has a first additional terminal, and the second antifuse has a second additional terminal electrically isolated from the first additional terminal;
a first pass-gate transistor connected between a first bitline for a column and the first additional terminal;
and
a second pass-gate transistor connected between the second additional terminal and a second bitline for the column, wherein gates of the first pass-gate transistor and the second pass-gate transistor are connected to the wordline;
and
selectively and individually performing operations directed to selected antifuses of selected cells in the array.

8 more elements

Dependencies are inferred from the claim text.

Memory cell including dual-antifuse device, memory structure, and operating method

Life of this patent

Memory cell including dual-antifuse device, memory structure, and operating method

Life of this patent

Abstract

Claims20