Semiconductor memory devices

A semiconductor memory device, comprising:

• a cell array structure including a plurality of memory cells and a plurality of first bonding pads electrically connected to the plurality of memory cells, respectively, the cell array structure including a cell array region on which the plurality of memory cells are provided and a first peripheral region adjacent the cell array region;
• a peripheral circuit structure including a plurality of peripheral circuits and a plurality of second bonding pads electrically connected to the plurality of peripheral circuits, respectively, the plurality of second bonding pads being bonded to the plurality of first bonding pads, respectively;
• and
• a passivation layer including a plurality of input/output pads and a plurality of dummy pads,
• wherein, when viewed in cross section, the cell array structure is between the passivation layer and the peripheral circuit structure,
• wherein the plurality of input/output pads overlap the first peripheral region of the cell array structure, and
• wherein the plurality of dummy pads overlap the cell array region of the cell array structure.

A semiconductor memory device, comprising:

• a cell array structure including a plurality of first bonding pads electrically connected to a plurality of memory cells, respectively, the cell array structure including a cell array region on which the plurality of memory cells are provided and a first peripheral region adjacent the cell array region, the cell array region including a bit-line connection region and a word-line connection region;
• and
• a peripheral circuit structure including a plurality of peripheral circuits and a plurality of second bonding pads that are electrically connected to the plurality of peripheral circuits, respectively, and are bonded to the plurality of first bonding pads, respectively,
• wherein the cell array structure includes:
• a lower dielectric layer including a first surface and a second surface that are opposite to each other;
• a stack structure including a plurality of word lines that are stacked in a direction perpendicular to the first surface of the lower dielectric layer;
• a vertical structure including a plurality of bit lines in the stack structure;
• an input/output plug in a dielectric layer on the stack structure;
• an input/output pad on the second surface of the lower dielectric layer on the first peripheral region, the input/output pad being electrically connected to the input/output plug;
• and
• a plurality of dummy pads on the second surface of the lower dielectric layer on the bit-line connection region and the word-line connection region.