Vertical gate-all-around (GAA) memory cell and method for forming the same

A method for forming a memory cell, comprising:

• patterning a first dielectric layer to form a pair of trenches respectively overlying and exposing a pair of lower conductors;
• depositing a second dielectric layer overlying the first dielectric layer and in the pair of trenches, wherein a pair of voids form in the second dielectric layer, respectively at the pair of trenches, and are sealed at completion of the depositing;
• opening the pair of voids after the depositing;
• forming a pair of middle conductors respectively filling the pair of voids;
• forming a pair of semiconductor channels respectively overlying the pair of middle conductors;
• and
• forming a pair of gate electrodes respectively on sidewalls of the pair of semiconductor channels;
• wherein the pair of voids form with different cross-sectional areas.

A method for forming a memory cell, comprising:

• patterning a dielectric layer to form a trench exposing a lower conductor;
• depositing an insulator layer lining the trench and only partially filling the trench;
• etching back the insulator layer to clear the insulator layer from a top surface of the dielectric layer;
• depositing a sacrificial layer overlying the dielectric layer and filling a remainder of the trench over the insulator layer after the etching back;
• performing a planarization to clear the sacrificial layer from the top surface of the dielectric layer;
• depositing an etch stop layer overlying the dielectric and sacrificial layers;
• patterning the etch stop layer to form an opening exposing the sacrificial layer;
• removing the sacrificial layer to partially clear the trench;
• forming a semiconductor structure in the opening with a bottom protrusion protruding into a portion of the insulator layer in the trench;
• and
• forming a gate electrode surrounding the semiconductor structure.