Hardware-based key generation and storage for cryptographic function

A method of data processing in a processor, said method comprising:

• receiving, by an execution unit of the processor, a key-generating instruction including an operand field, wherein the execution unit includes a key generation circuit, including:
• a working register for buffering a plurality of words of differing lengths;
• a plurality of different Advanced Encryption Standard (AES) key generation function circuits each coupled to receive a respective set of words from the working register, wherein the respective set of words each of the plurality of AES key generation function circuits is coupled to receive from the working register differs from any of the plurality of AES key generation function circuits, each of the plurality of different key generation circuits having a corresponding output;
• selection circuitry coupled to select between the corresponding outputs of the plurality of different AES key generation function circuits for storage in the working register;
• output circuitry;
• and
• a control circuit;
• and
• based on receiving the key-generating instruction, the execution unit executing the key-generating instruction, wherein the executing includes the control circuit causing one of the plurality of different AES key generation function circuits and the selection circuitry to iteratively apply a cryptographic function to a sequence of iteration inputs beginning with an encryption key obtained from at least one source register within an architected register file of the processor and storing, within the architected register file, a decryption key obtained from at least one iteration of the cryptographic function, wherein the decryption key is configured for decrypting ciphertext encrypted utilizing the encryption key;
• wherein a first of the plurality of different AES key generation function circuits implements a different key generation function than a second of the plurality of different AES key generation function circuits;
• and
• wherein the first of the plurality of different AES key generation function circuits implements a key generation function for a first key length and the second of the plurality of different AES key generation function circuits implements a key generation function for a second key length different from the first key length.

A design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• a processor, including:
• an instruction fetch circuit configured to fetch instructions;
• an architected register file including a plurality of registers for storing source and destination operands;
• and
• an execution unit for executing a key-generating instruction including an operand field, wherein the execution unit includes a key generation circuit, including:
• a working register for buffering a plurality of words of differing lengths;
• a plurality of different Advanced Encryption Standard (AES) key generation function circuits each coupled to receive a respective set of words from the working register, wherein the respective set of words each of the plurality of AES key generation function circuits is coupled to receive from the working register differs from any other of the plurality of AES key generation function circuits, each of the plurality of different key generation circuits having a corresponding output;
• selection circuitry coupled to select between the corresponding outputs of the plurality of different AES key generation function circuits for storage in the working register;
• output circuitry;
• and
• a control circuit that, responsive to a key-generating instruction, causes one of the plurality of different AES key generation function circuits and the selection circuitry to iteratively apply a cryptographic function to a sequence of iteration inputs beginning with an encryption key obtained from at least one source register within the architected register file indicated by the operand field, wherein a decryption key is configured for decrypting ciphertext encrypted utilizing the encryption key;
• wherein a first of the plurality of different AES key generation function circuits implements a different key generation function than a second of the plurality of different AES key generation function circuits;
• and
• wherein the first of the plurality of different AES key generation function circuits implements a first key generation function for a first key length and the second of the plurality of different AES key generation function circuits implements a second key generation function for a second key length different from the first key length.