Coding circuit and memory device including the same

A coding circuit comprising:

• an encoder circuit configured to generate parity by applying input data to a parity generating matrix and generate an input codeword by concatenating the input data and the parity;
• and
• a decoder circuit configured to detect and correct an error included in an output codeword based on a first syndrome, a second syndrome, and a third syndrome for identifying an error boundary between adjacent symbols of the output codeword, the first, second, and third syndromes being generated by applying the output codeword to the parity generating matrix,
• wherein the parity generating matrix includes a first syndrome generating matrix to generate the first syndrome, a second syndrome generating matrix to generate the second syndrome, and a third syndrome generating matrix to generate the third syndrome when the output codeword is applied during a read operation,
• wherein the first syndrome generating matrix includes a plurality of odd error decision rows to determine whether an odd number of errors exist and includes a plurality of error boundary decision rows to determine a target error boundary where the error occurred among a plurality of error boundaries,
• wherein the third syndrome generating matrix includes a plurality of columns corresponding to the plurality of error boundaries, and
• wherein the target error boundary is determined based on the error boundary decision rows, the second syndrome, and the third syndrome.

A memory device comprising:

• a memory cell array;
• and
• a coding circuit configured to provide an input codeword to the memory cell array by encoding input data, and to generate output data and a detection signal by decoding output codeword output from the memory cell array,
• wherein the coding circuit includes:
• an encoder circuit configured to generate parity by applying the input data to a parity generating matrix and generate the input codeword by concatenating the input data and the parity;
• and
• a decoder circuit configured to detect and correct an error included in the output codeword based on a first syndrome, a second syndrome, and a third syndrome for identifying an error boundary between adjacent symbols of the output codeword, the first, second, and third syndromes being generated by applying the output codeword to the parity generating matrix, wherein the encoder circuit comprises:
• a first concatenation circuit configured to concatenate the input data and padding data;
• a selection circuit configured to select an output of the first concatenation circuit or the output codeword;
• a parity generator configured to apply an output of the selection circuit to the parity generating matrix;
• and
• a second concatenation circuit configured to generate the input codeword by concatenating the input data and an output of the parity generator.

A memory device comprising:

• a memory cell array;
• and
• a coding circuit configured to provide an input codeword to the memory cell array by encoding input data, and to generate output data and a detection signal by decoding output codeword output from the memory cell array,
• wherein the coding circuit includes:
• an encoder circuit configured to generate parity by applying the input data to a parity generating matrix and generate the input codeword by concatenating the input data and the parity;
• and
• a decoder circuit configured to detect and correct an error included in the output codeword based on a first syndrome, a second syndrome, and a third syndrome for identifying an error boundary between adjacent symbols of the output codeword, the first, second, and third syndromes being generated by applying the output codeword to the parity generating matrix,
• wherein the parity generating matrix includes a first syndrome generating matrix to generate the first syndrome, a second syndrome generating matrix to generate the second syndrome, and a third syndrome generating matrix to generate the third syndrome when the output codeword is applied during a read operation,
• wherein the first syndrome generating matrix includes a plurality of odd error decision rows to determine whether an odd number of errors exist and includes a plurality of error boundary decision rows to determine a target error boundary where the error occurred among a plurality of error boundaries,
• wherein the third syndrome generating matrix includes a plurality of columns corresponding to the plurality of error boundaries, and
• wherein the target error boundary is determined based on the error boundary decision rows, the second syndrome, and the third syndrome.