SAR ADC bit storage upon reset
AssigneeCadence Design Systems, Inc.
InventorsChristopher George Moscone, Mark A. Summers, Chunkyun Seok
Life of this patent
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Abstract
Methods and systems are provided for operating an SAR ADC. The SAR ADC receives an analog signal and receives a first instance of conversion trigger signal. The SAR ADC, in response to receiving the first instance of the conversion trigger signal, generates a set of digital bit values corresponding to the analog signal. The SAR ADC, while one or more digital bit values corresponding to the analog signal are being generated, receives a second instance of the conversion trigger signal and temporarily stores the one or more digital bit values in response to receiving the second instance of the conversion trigger signal.
Claims20
A system comprising:
- a successive approximation register (SAR) analog-to-digital converter (ADC) configured to perform operations comprising:
- receiving an analog signal;
- receiving a first instance of conversion trigger signal;
- in response to receiving the first instance of the conversion trigger signal, generating a set of digital bit values corresponding to the analog signal;
- while one or more digital bit values corresponding to the analog signal are being generated, receiving a second instance of the conversion trigger signal;
- and
- temporarily storing the one or more digital bit values in response to receiving the second instance of the conversion trigger signal.
A method comprising:
- receiving, by a successive approximation register (SAR) analog-to-digital converter (ADC), an analog signal;
- receiving a first instance of conversion trigger signal;
- in response to receiving the first instance of the conversion trigger signal, generating a set of digital bit values corresponding to the analog signal;
- while one or more digital bit values corresponding to the analog signal are being generated, receiving a second instance of the conversion trigger signal;
- and
- temporarily storing the one or more digital bit values in response to receiving the second instance of the conversion trigger signal.
A non-transitory computer-readable medium comprising computer-readable instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
- receiving, by a successive approximation register (SAR) analog-to-digital converter (ADC), an analog signal;
- receiving a first instance of conversion trigger signal;
- in response to receiving the first instance of the conversion trigger signal, generating a set of digital bit values corresponding to the analog signal;
- while one or more digital bit values corresponding to the analog signal are being generated, receiving a second instance of the conversion trigger signal;
- and
- temporarily storing the one or more digital bit values in response to receiving the second instance of the conversion trigger signal.
Dependencies are inferred from the claim text.