US 12,726,208 B1 · Efficient clocking scheme for die-to-die connectivity

Abstract

An integrated circuit (IC) chip includes a first data receiver including first receiver circuitry to receive first data from a second IC chip. A second data receiver includes second receiver circuitry to receive second data from the second IC chip. Timing circuitry couples to the first receiver and the second receiver in a shared configuration. The timing circuitry generates a receive timing signal to time reception of the first data and the second data by the first and second receivers. The timing circuitry generates the receive timing signal through use of a phase adjustment circuit. The first and second receivers sample the first and second data in response to the receive timing signal. The timing circuitry includes a forwarded timing interface for transferring a forwarded timing signal between the IC chip and the second IC chip.

Claims19

Dependent claims

An integrated circuit (IC) chiplet, comprising:

a first number of multiple data receivers, each of the multiple data receivers comprising a clock input to receive a common clock signal;
wherein the first number of multiple data receivers are organized into subsets of data receivers, each subset of the subsets of data receivers comprising:
a second number of data receivers that is less than the first number of multiple data receivers, the second number of data receivers to receive data signals at substantially a same time;
and
phase adjustment circuitry that is shared solely by the second number of data receivers, the phase adjustment circuitry to generate a sampling clock signal by adjusting a timing of the common clock signal to sample data signals of the subsets of data receivers.

2 more elements

Dependencies are inferred from the claim text.

Efficient clocking scheme for die-to-die connectivity

Life of this patent

Efficient clocking scheme for die-to-die connectivity

Life of this patent

Abstract

Claims19