Digital delay line of a memory system and method of adjusting timing of clocks using thereof

A method of adjusting a timing of clocks within a memory system using a digital delay line including:

• a coarse delay line receiving a high-speed input clock;
• and
• a fine delay line transmitting an interface output clock to transceivers;
• wherein the coarse delay line is configured to perform clock division of a frequency of the high-speed input clock to a frequency of the interface output clock;
• wherein the coarse delay line comprises a dual-edge triggered flip-flop to produce a shifted divided clock and a clock mux configured to bypass the high-speed input clock when delay shifting is not performed;
• wherein the fine delay line is configured to provide a finer delay step size, the method comprising:
• counting clock position of high-speed input clock's edges within one unit interval of divided clock by a counter;
• generating edges of the divided clock based on a clock sub-unit interval position controlled by a delay code;
• calculating and re-calculating falling edge sub-unit interval position according to the delay code;
• and
• outputting a count value of the counter, by a dual edge triggered flip-flop, when the count value of the counter matches a rising or falling edge position to produce shifted divided clock.