Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells

A multi-chip package comprising:

• an interconnection scheme comprising:
• a first interconnection metal layer,
• a first polymer layer over the first interconnection metal layer,
• a second interconnection metal layer extending horizontally on a top surface of the first polymer layer and further extending downwards into a first opening in the first polymer layer, wherein the second interconnection metal layer comprises a first copper layer extending horizontally over the top surface of the first polymer layer and further extending downwards into the first opening in the first polymer layer, wherein the first copper layer has a sidewall over the top surface of the first polymer layer, wherein the second interconnection metal layer further comprises a first adhesion metal layer at a bottom of the first copper layer and not at the sidewall of the first copper layer,
• a second polymer layer on the second interconnection metal layer and first polymer layer and at a top of the interconnection scheme, and
• a plurality of first metal bumps each at the top of the interconnection scheme, extending horizontally on a top surface of the second polymer layer, further extending downwards into a second opening in the second polymer layer and in contact with a top surface of the second interconnection metal layer, wherein each of the plurality of first metal bumps comprises a second copper layer extending horizontally over the top surface of the second polymer layer and further extending downwards into the second opening in the second polymer layer, wherein the second copper layer has a sidewall over the top surface of the second polymer layer, wherein said each of the plurality of first metal bumps further comprises a second adhesion metal layer at a bottom of the second copper layer, on the top surface of the second polymer layer and the top surface of the second interconnection metal layer and not at the sidewall of the second copper layer;
• a third polymer layer under the first interconnection scheme and at a bottom of the multi-chip package;
• a second metal bump at the bottom of the multi-chip package, extending on a bottom surface of the third polymer layer, further extending upwards into a third opening in the third polymer layer and in contact with a bottom surface of the first interconnection metal layer, wherein the second metal bump comprises a third copper layer extending under the bottom surface of the third polymer layer and further extending upwards into the third opening in the third polymer layer, wherein the third copper layer has a sidewall under the bottom surface of the third polymer layer, wherein the second metal bump further comprises a third adhesion metal layer at a top of the third copper layer and not at the sidewall of the third copper layer, wherein the third adhesion metal layer is between the third copper layer and the bottom surface of third polymer layer, between the third copper layer and the bottom surface of first interconnection metal layer and on the bottom surface of the third polymer layer and the bottom surface of the first interconnection metal layer, wherein the second metal bump further comprises a first tin-containing cap under the third copper layer;
• a plurality of semiconductor integrated-circuit (IC) chips over the interconnection scheme and at a same horizontal level as each other or one another, wherein each of the plurality of semiconductor integrated-circuit (IC) chips comprises a third metal bump at a bottom of said each of the plurality of semiconductor integrated-circuit (IC) chips and protruding from a bottom surface of said each of the plurality of semiconductor integrated-circuit (IC) chips, wherein the third metal bump is bonded to one of the plurality of first metal bumps as a bonded contact, wherein the third metal bump comprises a fourth copper layer and a second tin- containing cap under the fourth copper layer and bonded to said one of the plurality of first metal bumps;
• and
• a fourth polymer layer on the interconnection scheme and at the same horizontal level as the plurality of semiconductor integrated-circuit (IC) chips.