Driver and transmitter

A transmitter, comprising a driver, an encoder, an actuator and a control circuit, wherein

• the control circuit is respectively connected to the driver, the encoder and the actuator and configured to monitor and adjust the operation states of the driver, the encoder and the actuator;
• the encoder is connected to the driver and configured to input a first level signal to the driver;
• the driver is configured to convert the first level signal into a second level signal;
• the actuator is connected to the driver and configured to receive the second level signal and execute an action corresponding to the second level signal;
• and
• the driver comprises:
• an n-type metal-oxide-semiconductor field-effect transistor differential circuit, a p-type metal-oxide-semiconductor field-effect transistor differential circuit and a power supply, and an auxiliary voltage adjusting circuit,
• the power supply is connected to a source electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit, a drain electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit is connected to a drain electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit, and a source electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit is grounded,
• a gate electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit and a gate electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit are configured to receive the first level signal, the p-type metal-oxide-semiconductor field-effect transistor differential circuit and the n-type metal-oxide-semiconductor field-effect transistor differential circuit are configured to convert the first level signal into the second level signal, and
• the drain electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit and the drain electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit are configured to output the second level signal,
• the auxiliary voltage adjusting circuit is connected to the drain electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit and the drain electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit;
• and
• when detecting that the drain electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit and a field-effect transistor in the n-type metal-oxide-semiconductor field-effect transistor differential circuit are in an off state, the auxiliary voltage adjusting circuit provides a common mode voltage and outputs a signal, wherein the signal is obtained by superimposing the second level signal on the common mode voltage,
• wherein the n-type metal-oxide-semiconductor field-effect transistor differential circuit comprises:
• a first n-type metal-oxide-semiconductor field-effect transistor and a second n-type metal-oxide-semiconductor field-effect transistor;
• and
• a gate electrode of the first n-type metal-oxide-semiconductor field-effect transistor is configured to receive a binary least significant bit positive signal in the first level signal, and a gate electrode of the second n-type metal-oxide-semiconductor field-effect transistor is configured to receive a binary least significant bit negative signal in the first level signal.

A data interface circuit, comprising a driver, wherein the driver comprises:

• an n-type metal-oxide-semiconductor field-effect transistor differential circuit, a p-type metal-oxide-semiconductor field-effect transistor differential circuit and a power supply, and an auxiliary voltage adjusting circuit,
• the power supply is connected to a source electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit, a drain electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit is connected to a drain electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit, and a source electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit is grounded,
• a gate electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit and a gate electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit are configured to receive the first level signal, the p-type metal-oxide-semiconductor field-effect transistor differential circuit and the n-type metal-oxide-semiconductor field-effect transistor differential circuit are configured to convert the first level signal into the second level signal, and
• the drain electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit and the drain electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit are configured to output the second level signal,
• the auxiliary voltage adjusting circuit is connected to the drain electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit and the drain electrode of the n-type metal-oxide-semiconductor field-effect transistor differential circuit;
• and
• when detecting that the drain electrode of the p-type metal-oxide-semiconductor field-effect transistor differential circuit and a field-effect transistor in the n-type metal-oxide-semiconductor field-effect transistor differential circuit are in an off state, the auxiliary voltage adjusting circuit provides a common mode voltage and outputs a signal, wherein the signal is obtained by superimposing the second level signal on the common mode voltage,
• wherein the n-type metal-oxide-semiconductor field-effect transistor differential circuit comprises:
• a first n-type metal-oxide-semiconductor field-effect transistor and a second n-type metal-oxide-semiconductor field-effect transistor;
• and
• a gate electrode of the first n-type metal-oxide-semiconductor field-effect transistor is configured to receive a binary least significant bit positive signal in the first level signal, and a gate electrode of the second n-type metal-oxide-semiconductor field-effect transistor is configured to receive a binary least significant bit negative signal in the first level signal.