Delay clock circuit, signal transmission device and a method for determining delay

Abstract

The present application provides a delay clock circuit, a signal transmission device and a method for determining delay, and relates to the field of circuit technologies. The delay clock circuit includes: a self-activation module, including a first inverter and a delay circuit, and used for generating a self-activation clock signal, where the first inverter is connected to an input end of the delay circuit and an output end of the delay circuit respectively; a first counter, connected to the self-activation module, and used for starting to work under a drive of the self-activation clock signal and a start counting signal and stopping working under a drive of a stop counting signal to obtain a first counting result within a preset duration; and a count processing module, connected to the first counter, and used for obtaining a delay of the delay circuit based on the preset duration and the first counting result. The present application can perform calculations based on an accumulated delay counted by the first counter to obtain an accurate delay of the delay circuit. Therefore, an application requirement of a controllable and flexible adjustable delay of the delay circuit in different scenarios is satisfied, and stable and reliable data transmission is achieved.

Dependencies are inferred from the claim text.