Charge injection-related and switching error-related offset reduction by local chopping of switched-capacitor circuits

A differential switched-capacitor circuit comprising:

• a pair of input sampling capacitors;
• a switching circuit including a plurality of charge transfer switches that alternatively charge the pair of input sampling capacitors from a differential input in a first phase of a reference sampling clock and transfer charge from the pair of input sampling capacitors in a second phase of the reference sampling clock;
• and
• a chopping circuit that alternates connections to each terminal of at least some of the charge transfer switches of the switching circuit between differential pairs of signals through the switching circuit, wherein the chopping circuit is operated at a chopping frequency different from a frequency of the reference sampling clock, whereby a DC offset caused by charge-injection asymmetry in the differential switched-capacitor circuit due to the reference sampling clock coupling through the charge transfer switches of the switching circuit is removed by modulating a charge injection of the switching circuit away from DC.

A method of reducing DC offset due to charge injection asymmetry in a differential switched-capacitor circuit, the method comprising:

• operating the differential switched-capacitor circuit to sample a differential input signal with a pair of input sampling capacitors at a reference sampling frequency, whereby the DC offset is caused by edges of a first control operating the differential switched-capacitor circuit at the reference sampling frequency coupling through one or more charge transfer switches of the differential switched-capacitor circuit and accumulating to produce the DC offset, wherein the differential switched-capacitor circuit is a differential switched-capacitor integrator or gain-stage including a pair of input sampling capacitors, wherein the one or more charge transfer switches alternatively charge the pair of input sampling capacitors from a differential input in a first phase of a reference sampling clock and transfer charge from the pair of input sampling capacitors in a second phase of the reference sampling clock to a pair of feedback capacitors coupled between outputs and inputs of a differential amplifier;
• and
• chopping switching paths of each terminal of the one or more charge transfer switches to alternate connections of each terminal of the one or more charge transfer switches with a chopper operating at a chopping frequency different from the reference sampling frequency, wherein the chopper alternates connections to at least some of the one or more charge transfer switches between differential pairs of signals through the differential switched-capacitor circuit, whereby the chopper modulates the charge-injection of the one or more charge transfer switches away from DC.