Semiconductor device with input protection

A semiconductor device comprising:

• an analog input channel having an input pad and an input node,
• an electrostatic discharge (ESD) protection structure, comprising:
• a resistor with a first terminal connected to the input pad and a second terminal connected to the input node;
• a first diode having an anode connected to the first terminal of the resistor;
• and
• a second diode having a cathode connected to the first terminal of the resistor;
• an active clamp circuit connected between the input node and a power rail, the active clamp circuit comprising:
• a clamp transistor having controlled terminals and a gate, the controlled terminals being connected between the input node and the power rail, the clamp transistor being a metal oxide semiconductor (MOS) transistor;
• and
• a comparator arranged to compare a voltage at the input node with a comparison voltage, the comparator having an output connected to the gate of the clamp transistor to turn on the clamp transistor to apply a clamp voltage to the input node when the voltage at the input node passes the comparison voltage.

An integrated circuit, comprising:

• a load circuit having an input;
• a first analogue input channel having a first input pin and a first input node connected to the input of the load circuit through a first transmission gate,
• a second analogue input channel having a second input pin and a second input node connected to the input of the load circuit through a second transmission gate,
• wherein the first analogue input channel comprises:
• an electrostatic discharge (ESD) protection structure coupled between the first input pin and the first input node, the ESD protection structure including:
• a resistor having a first terminal coupled to the first input pin and a second terminal coupled to the first input node, a first diode having an anode coupled to the first terminal of the resistor and a cathode coupled to VDD, and a second diode having an anode coupled to VSS and a cathode coupled to the first terminal of the resistor;
• a high-side comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the high-side comparator coupled to the second terminal of the resistor, and the second input terminal of the high-side comparator coupled to VDD;
• a high-side clamp transistor having a first terminal, a second terminal, and a control terminal, the control terminal of the high-side clamp transistor coupled to the output terminal of the high-side comparator, the first terminal of the high-side clamp transistor coupled to VDD, and the second terminal of the high-side clamp transistor coupled to the second terminal of the resistor and coupled to an input of the first transmission gate;
• a low-side comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the low-side comparator coupled to the second terminal of the resistor, and the second input terminal of the low-side comparator coupled to VSS;
• and
• a low-side clamp transistor having a first terminal, a second terminal, and a control terminal, the control terminal of the low-side clamp transistor coupled to the output terminal of the low-side comparator, the first terminal of the low-side clamp transistor coupled to VSS, and the second terminal of the low-side clamp transistor coupled to the second terminal of the resistor and coupled to the input of the first transmission gate.