Memory device, memory system, memory controller, and operation method

A memory system, comprising:

• one or more memory devices, wherein each of the one or more memory devices comprises:
• a memory cell array comprising memory cells that store a plurality of memory bits, the plurality of memory bits corresponding to a plurality of orders of read voltages, and a preset number of the memory cells forming a code word;
• and
• a peripheral circuit coupled with the memory cell array and configured to:
• acquire a first result of at least one code word corresponding to a target read voltage of a target order, wherein the first result indicates the number of flipped bits of the at least one code word in two read results corresponding to a first read voltage and a second read voltage, and a difference between the first read voltage and the second read voltage is less than a preset voltage;
• acquire a predicted valley bottom voltage of the target order according to the first result of the at least one code word corresponding to the target read voltage of the target order and a level in which the target order is located;
• and
• determine a target valley bottom voltage of the target order based on the predicted valley bottom voltage of the target order, wherein the target valley bottom voltage is taken as a read voltage for a read operation performed on the at least one code word;
• and
• a memory controller coupled with the one or more memory devices and configured to control the one or more memory devices.

A memory controller, comprising:

• a control unit configured to:
• acquire a first result of at least one code word corresponding to a target read voltage of a target order, wherein the first result indicates the number of flipped bits of the at least one code word in two read results corresponding to a first read voltage and a second read voltage, and a difference between the first read voltage and the second read voltage is less than a preset voltage, wherein the memory controller is coupled with at least one memory device, wherein the at least one memory device comprises memory cells that store a plurality of memory bits, wherein the plurality of memory bits correspond to a plurality of orders of read voltages, and wherein a preset number of the memory cells forming a code word;
• acquire a predicted valley bottom voltage of the target order according to the first result of the at least one code word corresponding to the target read voltage of the target order and a level in which the target order is located;
• and
• determine a target valley bottom voltage of the target order based on the predicted valley bottom voltage of the target order, wherein the target valley bottom voltage is taken as a read voltage for a read operation performed on the at least one code word.