Sub-block mode back pattern effect compensation

A method for operating a memory system, the method comprising:

• determining a first degree of programming in an unselected sub-block of a block, the block comprising a plurality of NAND strings and word lines, the block comprising the unselected sub-block and a selected sub-block, the selected sub-block comprising a first set of contiguous word lines, the unselected sub-block comprising a second set of contiguous word lines;
• applying a program verify voltage to a selected word line in the selected sub-block, the program verify voltage having a magnitude that depends on the first degree of programming in the unselected sub-block, the selected word line connected to selected memory cells;
• and
• determining results of verifying the selected memory cells in response to application of the program verify voltage;
• determining a second degree of programming in the unselected sub-block of the block prior to a read while the selected memory cells connected to the selected word line still store data verified with the program verify voltage having the magnitude that depended on the first degree of programming in the unselected sub-block at a time of program verify, the program verify voltage being used to verify a first data state;
• applying a read reference voltage to the selected word line, the read reference voltage having a magnitude that depends on the second degree of programming in the unselected sub-block when applying the read reference voltage to the selected word line, the read reference voltage being used to read the first data state;
• and
• sensing the selected memory cells in response to application of the read reference voltage.

A non-volatile storage device, comprising:

• a three-dimensional memory structure having blocks, each block having NAND strings and word lines connected to the NAND strings;
• and
• one or more control circuits in communication with the three-dimensional memory, the one or more control circuits configured to:
• operate the memory structure in a sub-block mode in which sub-blocks of a block are erased and programmed independently, each sub-block being a unit of erase;
• determine a magnitude for a program verify voltage for a selected word line in a selected sub-block in a selected block during the sub-block mode, the magnitude for the program verify voltage depends on a first degree of programming of the word lines in one or more unselected sub-blocks in the selected block when the program verify voltage is applied to the selected word line;
• apply the program verify voltage having the magnitude that depends on the first degree of programming of the word lines in the one or more unselected sub-blocks to the selected word line during the sub-block mode;
• sense selected memory cells connected to the selected word line in response to application of the program verify voltage to the selected word line;
• determine a second degree of programming in the one or more unselected sub-blocks of the selected block prior to a read while the selected memory cells connected to the selected word line still store data verified with the program verify voltage having the magnitude that depended on the first degree of programming in the one or more unselected sub-blocks at a time of program verify, the program verify voltage being used to verify a first data state;
• apply a read reference voltage to the selected word line, the read reference voltage having a magnitude that depends on the second degree of programming in the one or more unselected sub-blocks when applying the read reference voltage to the selected word line, the read reference voltage being used to read the first data state;
• and
• sense the selected memory cells in response to application of the read reference voltage.