Leakage compensation circuit for content addressable memory (CAM) cell

A leakage compensation content addressable memory (CAM) circuit, comprising:

• at least one CAM cell configured to store a bit value;
• and
• at least one compensation CAM cell configured to store the bit value of the CAM cell and to cancel leakage current of the CAM cell, wherein:
• the CAM cell comprises:
• a first CAM cell transistor;
• a second CAM cell transistor, wherein a gate of the second CAM cell transistor is coupled to a first word line, and a source of the second CAM cell transistor is coupled to a first bit line of the CAM cell;
• a third CAM cell transistor, wherein a gate of the third CAM cell transistor is coupled to a second word line, and a source of the third CAM cell transistor is coupled to a second bit line of the CAM cell;
• a fourth CAM cell transistor, wherein a gate of the fourth CAM cell transistor is coupled to drains of the first, second and third CAM cell transistors;
• a fifth CAM cell transistor, wherein a gate of the fifth CAM cell transistor is coupled to the first word line, and a source of the fifth CAM cell transistor is coupled to a third bit line of the CAM cell;
• and
• a sixth CAM cell transistor, wherein a gate of the sixth CAM cell transistor is coupled to the second word line and a source of the sixth CAM cell transistor is coupled to a fourth bit line of the CAM cell, and wherein a gate of the first CAM cell transistor is coupled to drains of the fourth, fifth and sixth CAM cell transistors, wherein the first and fourth CAM cell transistors are first type transistors and the second, third, fifth and sixth CAM cell transistors are second type transistors;
• and
• the compensation CAM cell comprises:
• a first compensation CAM cell transistor;
• a second compensation CAM cell transistor, wherein a gate of the second compensation CAM cell transistor is coupled to a third word line, and a source of the second compensation CAM cell transistor is coupled to a first bit line of the compensation CAM cell;
• a third compensation CAM cell transistor, wherein a gate of the third compensation CAM cell transistor is coupled to a fourth word line, and a source of the third compensation CAM cell transistor is coupled to a second bit line of the compensation CAM cell,
• a fourth compensation CAM cell transistor, wherein a gate of the fourth compensation CAM cell transistor is coupled to drains of the first, second and third compensation CAM cell transistors;
• a fifth compensation CAM cell transistor, wherein a gate of the fifth compensation CAM cell transistor is coupled to the third word line, and a source of the fifth compensation CAM cell transistor is coupled to a third bit line of the compensation CAM cell;
• and
• a sixth compensation CAM cell transistor, wherein a gate of the sixth compensation CAM cell transistor is coupled to the fourth word line and a source of the sixth compensation CAM cell transistor is coupled to a fourth bit line of the compensation CAM cell, and wherein a gate of the first compensation CAM cell transistor is coupled to drains of the fourth, fifth and sixth compensation CAM cell transistors, wherein the first and fourth compensation CAM cell transistors are the second type transistors and the second, third, fifth and sixth compensation CAM cell transistors are the first type transistors.