Semiconductor memory devices and electronic devices including the semiconductor memory devices

An electronic device comprising:

• a system-on-chip (SoC) including a memory controller, a display controller, and a graphic processing unit (GPU) configured to generate a plurality of image data by rendering at least one object;
• a semiconductor memory device connected to the SoC through the memory controller;
• and
• a display device connected to the SoC through the display controller,
• wherein the semiconductor memory device comprises:
• a memory cell array including a plurality of volatile memory cells coupled to a plurality of word-lines and a plurality of bit-lines, the memory cell array configured to store the plurality of image data;
• and
• a data first-in/first-out (FIFO) circuit including a plurality of data FIFO buffers configured to sequentially store read image data that is read from the memory cell array in each of a plurality of read operations, and
• wherein, when a second frame to be displayed in the display device comprises first image data that is the same image data as is in one of a predetermined range of previous first frames, the semiconductor memory device is configured to provide, via the memory controller and the display controller, the display device with the first image data from one of the plurality of data FIFO buffers.