Memory device having unity buffers with output current limiters
AssigneeMicron Technology, Inc.
InventorsFerdinando Bedeschi, Pierguido Garofalo, Michele Maria Venturini
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Abstract
Systems, methods, and apparatus related to unity buffers in memory devices. In one approach, a memory device includes memory arrays having memory cells. The memory device includes access lines to access the memory cells. The memory device includes unity buffers to drive the access line loads. Each buffer has an output current limiter that limits current flow when driving a voltage on the access lines. By limiting the current, the current limiter provides improved frequency response and operating stability for the buffer without the need for a compensation net.
Claims20
An apparatus comprising:
- a memory array including memory cells;
- access lines configured to access the memory cells;
- and
- a buffer comprising:
- a differential stage having an input, the input to the differential stage is a non-inverting input;
- an output stage having an output responsive to the input;
- and
- a current limiter configured to couple the output to at least one first access line, wherein the current limiter is configured to limit current flow associated with driving a voltage on the first access line.
An apparatus comprising:
- a differential transistor pair including a first transistor having a gate coupled to an inverting input, and a second transistor having a gate coupled to a non-inverting input;
- an n-channel transistor having a gate coupled to a current terminal of the second transistor;
- and
- a current limiter coupled to a current terminal of the n-channel transistor, wherein the current limiter is configured to limit current flow when driving a load coupled to an output of the current limiter, and wherein the current terminal of the n-channel transistor is coupled to provide a feedback signal to the inverting input.
A method comprising:
- forming a communication interface configured to receive a read or write command from a host;
- forming a unity buffer in a semiconductor substrate, the unity buffer configured to generate an output proportional to an input;
- forming circuitry in the semiconductor substrate, the circuitry configured to, in response to receiving the command, provide an input on a non-inverting input of the unity buffer;
- forming a three-dimensional memory array above the semiconductor substrate, the memory array comprising at least one memory cell;
- forming an access line in the memory array, wherein the access line is configured to access the memory cell of the memory array;
- forming circuitry in the semiconductor substrate configured to drive a voltage on the access line using the generated output;
- and
- forming a current limiter configured to limit a current flow when driving the voltage, wherein the current limiter is coupled in series between the output of the unity buffer and the access line;
- wherein the current limiter comprises a transistor coupled between the output of the unity buffer and the access line, and wherein the transistor has a gate coupled to the input of a differential stage.
Dependencies are inferred from the claim text.