Bipolar decoders for nonvolatile memory

A method, comprising:

• forming on a first die a bipolar decoder circuit for a first set of control lines of a cross-point memory array of nonvolatile memory cells each connected between one of the first set of control lines and one of a second set of control lines, comprising:
• forming a plurality of positive voltage select switches each configured to supply a positive voltage level to a corresponding one of the first set of control lines, including forming first and second subsets of the plurality of positive voltage select switches on the first die;
• forming a plurality of negative voltage select switches each configured to supply a negative voltage level to a corresponding one of the first set of control lines, including forming a first subset of the plurality of negative voltage select switches on the first die between the first and second subsets of the plurality of positive voltage select switches;
• and
• forming a plurality of metal lines running over the positive voltage select switches and the negative voltage select switches, each of the metal lines connecting a corresponding one of either the positive voltage select switches or the negative voltage switches to a connection for the corresponding one of the first set of control lines, the connections located over a central region of the first die.

A memory device, comprising:

• a nonvolatile memory cell structure that includes nonvolatile memory cells in a cross-point arrangement, each memory cell having a programmable resistive element and connected between one of a plurality of first control lines and one of a plurality of second control lines;
• and
• one or more control circuits connected to the memory cell structure, comprising:
• a plurality of first decoding switches each configured to bias a corresponding one of the first control lines to positive voltage levels;
• a plurality of second decoding switches each configured to bias a corresponding one of the first control lines to negative voltage levels, a first subset of a plurality of the second decoding switches located on a die between a first subset of the first decoding switches and a second subset of the first decoding switches, each of the first subset the first decoding switches and the second of the first decoding switches comprising multiple ones of the first decoding switches;
• and
• a plurality of routing lines each connecting a corresponding one of either the first decoding switches or the second decoding switches to a corresponding connection point for one of the first control lines, the connection points located over the first subset of the second decoding switches.