Semiconductor memory device

A memory system comprising:

• a semiconductor memory device;
• and
• a memory controller,
• wherein
• the semiconductor memory device includes:
• a first pad being capable of transmitting or receiving a first timing signal to or from the memory controller;
• a second pad being capable of receiving a data signal from the memory controller in response to the first timing signal, and transmitting the data signal to the memory controller in accordance along with the first timing signal;
• a third pad being capable of receiving a second timing signal from the memory controller;
• a fourth pad being capable of receiving control information from the memory controller in response to the second timing signal;
• a memory cell array including a string in which a plurality of memory cell transistors are connected in series;
• a sense amplifier connected to the memory cell array;
• a first register connected to the sense amplifier and being capable of storing data read from the memory cell array;
• a second register being capable of storing first control information;
• a third register being capable of storing second control information;
• a fourth register storing being capable of storing third control information;
• and
• a control circuit being capable of executing a data-out operation of outputting the data stored in the first register from the first pad to the memory controller,
• upon receipt of plural cycles of inputs to the fourth pad in response to the second timing signal, the one of the second to fourth registers being selected based on a first part of the plural cycles of the inputs to the fourth pad, the received control information corresponding to a second part of the plural cycles of the inputs to the fourth pad being stored into the selected one of the second to fourth registers.

A semiconductor memory device comprising:

• a first pad for transmitting or receiving a first timing signal to or from an external memory controller;
• a second pad for receiving a data signal from the external memory controller in response to the first timing signal, and transmitting the data signal to the external memory controller in accordance along with the first timing signal;
• a third pad for receiving a second timing signal from the external memory controller;
• a fourth pad for receiving control information from the external memory controller in response to the second timing signal;
• a memory cell array including a string in which a plurality of memory cell transistors are connected in series;
• a sense amplifier connected to the memory cell array;
• a first register connected to the sense amplifier and being capable of storing data read from the memory cell array;
• a second register configured to store first control information;
• a third register configured to store second control information;
• a fourth register storing being capable of storing third control information;
• and
• a control circuit configured to execute
• a data-out operation of outputting first data stored in the first register from the first pad to the external memory controller, and
• a data-input operation of inputting second data received from the fourth pad into one of the second to fourth registers upon receipt of plural cycles of inputs to the fourth pad in response to the second timing signal, the one of the second to fourth registers being selected based on a first part of the plural cycles of the inputs to the fourth pad, the received second data corresponding to a second part of the plural cycles of the inputs to the fourth pad being stored into the selected one of the second to fourth registers.