Memory device, operation method of the same and memory system

An operation method, suitable for a memory device, comprising:

• receiving, by a memory array of the memory device, a storage data and an address data;
• activating, by an array control circuit of the memory device, a voltage generator of the memory device, in a programming stage of the memory array, so as to generate a first control voltage to the memory array;
• generating, by the array control circuit, a temporary address, in the programming stage, so as to control a first array of the memory array to store the storage data and the address data in a first programming step according to the temporary address and the first control voltage;
• activating, by the array control circuit, the voltage generator, in an idle stage of the memory array, so as to generate a second control voltage to the memory array;
• controlling, by the array control circuit, a second array of the memory array to store the storage data in a second programming step according to the address data and the second control voltage, in the idle stage;
• and
• controlling, by the array control circuit, the first array to perform an erasing operation, in the idle stage,
• wherein a voltage value of the first programming step is greater than a voltage value of the second programming step.

A memory system, comprising a plurality of memory devices, wherein each of the plurality of memory devices comprises:

• a memory array;
• a voltage generator, coupled to the memory array;
• and
• an array control circuit, coupled to the memory array and the voltage generator,
• wherein the memory array of at least one first memory device among the plurality of memory devices is configured as a first array, and the memory array of at least one second memory device among the plurality of memory devices is configured as a second array,
• wherein in a programming stage of the memory system, the array control circuit of the at least one first memory device is configured to control the voltage generator of the at least one first memory device to generate a first control voltage to the first array, and is configured to generate a temporary address to the first array to control the first array to store a storage data and an address data in a first programming step according to the temporary address and the first control voltage,
• wherein in an idle stage of the memory system, the array control circuit of the at least one second memory device is configured to control the voltage generator of the at least one second memory device to generate a second control voltage to the second array, and is configured to control the second array to store the storage data in a second programming step according to the address data and the second control voltage, and the array control circuit of the at least one first memory device is configured to control the first array to perform an erasing operation,
• wherein a voltage value of the first programming step is greater than a voltage value of the second programming step.