Memory, operation method thereof and memory system

A memory system, comprising:

• a memory device, comprising:
• a memory cell array comprising memory strings, wherein each of the memory strings comprises top select transistors and memory cells, and the top select transistors are located on a side of the memory cells;
• top select gate lines coupled to the top select transistors;
• word lines coupled to the memory cells;
• and
• a peripheral circuit coupled to the top select gate lines and the word lines, and configured to:
• apply a first pulse to a first word line of the word lines, such that a voltage of the first word line reaches a first target voltage at a first time instant;
• and
• apply a second pulse to a first top select gate line of the top select gate lines and which is adjacent to the first word line, such that a voltage of the first top select gate line reaches a second target voltage at a second time instant, wherein the second time instant is later than the first time instant;
• and
• a memory controller coupled to the memory device and configured to control the memory device.

An operation method of a memory device, wherein the memory device comprises a memory cell array and a peripheral circuit coupled to the memory cell array, the memory cell array comprises memory strings, and each of the memory strings comprises memory cells and top select transistors;

• word lines are coupled to the memory cells, and select gate lines are coupled to the top select transistors;
• and
• the operation method comprises:
• applying a first pulse to a first word line of the word lines, such that a voltage of the first word line reaches a first target voltage at a first time instant;
• and
• applying a second pulse to a first top select gate line of the top select gate lines and which is adjacent to the first word line, such that a voltage of the first top select gate line reaches a second target voltage at a second time instant, wherein the second time instant is later than the first time instant.