Semiconductor memory device and control method of semiconductor memory device

A semiconductor memory device having first and second physical planes each including a plurality of physical blocks of memory cells, the semiconductor memory device comprising:

• a first register in which a first physical block address is to be stored;
• a second register in which a second physical block address associated with the first physical block address is to be stored;
• a third register in which one or more third physical block addresses are to be stored;
• and
• an address registration unit including a first circuit configured to compare the first physical block address stored in the first register with the third physical block addresses stored in the third register and store the first physical block address in the second register as the second physical block address if the first physical block address does not match any of the third physical block addresses, and a second circuit configured to convert the first physical block address into another physical block address that is stored in the second register as the second physical block address when the first physical block address matches one of the third physical block addresses.