Controlling a data processing array using an array controller

An integrated circuit, comprising:

• a data processing array including a plurality of compute tiles each having a processor, a direct memory access circuit, and a stream switch coupled to other stream switches in adjacent compute tiles, wherein the data processing array is subdivided into a first partition including a first subset of the plurality of compute tiles and a second partition including a second subset of the plurality of compute tiles;
• a first array controller adapted to configure the first partition to implement a first application, wherein the first application specifies kernels executable by the processors of the first partition and first stream channels implemented by the stream switches that convey data to the first subset of the plurality of compute tiles of the first partition;
• and
• a second array controller adapted to configure the second partition to implement a second application, wherein the second application specifies kernels executable by the processors of the second partition and second stream channels implemented by the stream switches that convey data to the second subset of the plurality of compute tiles of the second partition;
• wherein the first array controller and the second array controller each is configured to initiate execution of workloads in the respective partitions by implementing different modes of data movement in the respective partitions for different ones of the workloads by, at least in part,
• programming the direct memory access circuits of the plurality of compute tiles of the respective partitions to convey a number of different feature maps and a number of different weights over the stream channels for distribution to different ones of the plurality of compute tiles for the different modes of data movement, wherein each mode of data movement varies at least one of the number of different feature maps or the number of different weights conveyed.