Computing architecture

An apparatus comprising:

• an array of compute circuits;
• a memory;
• a decoder circuitry to decode a single instruction into a decoded single instruction, the single instruction comprising a program counter field to identify a first of one or more functions to be performed using the array of compute circuits, a first address field to identify a location of first operand data to be used in the one or more functions, a second address field to identify a location of second operand data to be used in the one or more functions, a third address field to identify a destination for an output of the one or more functions, and a dense core address field to identify an address of a dense compute core to perform the one or more functions, wherein the single instruction corresponds to a request to offload the one or more functions from a sparse compute core to the dense compute core;
• and
• an execution circuit to execute the decoded single instruction according to the fields.

A method comprising:

• receiving an offload request at a particular one of a set of dense compute cores from a particular one of a set of sparse compute cores, wherein the set of dense compute cores and the set of sparse compute cores are interconnected in a network, and one or more of the set of dense compute cores and one or more of the set of sparse compute cores are present on a common die;
• performing a portion of a workload at the particular dense compute core based on the offload request, wherein the workload is associated with a graph data structure;
• and
• returning a result the portion of the workload to shared memory accessible to the particular sparse compute core.