Adaptive cache memory buffer register architecture

An apparatus comprising:

• means for incrementing a write hit-miss state based on a write address validation state and a write data validation state;
• means for incrementing a read hit-miss state based on a read address validation state and a read data validation state;
• means for computing a net mode count based on the write hit-miss state and the read hit-miss state;
• means for comparing the net mode count to a mode threshold value to update a plurality of mode toggle states;
• and
• means for generating an adaptive cache memory buffer register reassignment based on the plurality of mode toggle states.

A method comprising:

• incrementing a write hit-miss state based on a write address validation state and a write data validation state;
• incrementing a read hit-miss state based on a read address validation state and a read data validation state;
• computing a net mode count based on the write hit-miss state and the read hit-miss state;
• comparing the net mode count to a mode threshold value to update a plurality of mode toggle states;
• and
• generating an adaptive cache memory buffer register reassignment based on the plurality of mode toggle states.