Simulation apparatus, simulation method, and non-transitory computer readable medium
AssigneeRenesas Electronics Corporation
InventorsMasahiro Doi, Eiichi Arai, Tomoki Yonehana
Life of this patent
Estimating the term…
Abstract
A simulation apparatus includes a loop instruction sequence detector and an instruction computing section. The loop instruction sequence detector detects a loop instruction sequence included in a target program and generates a loop instruction sequence detection signal. When the loop instruction sequence detection signal is generated, the instruction computing section executes the loop instruction sequence once and generates a simulation elapsed time required for executing the loop instruction sequence a predetermined number of times.
Claims20
A simulation apparatus comprising a CPU model,
- wherein the CPU model comprises:
- an instruction controller including an instruction decoder configured to decode an instruction included in a program to be simulated and to generate a decode result;
- a loop instruction sequence detector including a loop instruction sequence pattern storage configured to store a loop instruction sequence pattern defining a loop instruction sequence to be repeatedly executed, and an instruction comparator configured to sequentially compare an instruction included in the program to be simulated with the loop instruction sequence pattern and to generate a loop instruction sequence detection signal indicating that a plurality of instructions included in the program to be simulated match the loop instruction sequence pattern;
- and
- an instruction computing section including an instruction executing section configured an to execute instruction included in the program to be simulated according to the decode result, an elapsed time controller configured to output a simulation elapsed time for which the instruction executing section executes an instruction included in the program to be simulated, and a loop instruction sequence elapsed time storage configured to store a loop instruction sequence elapsed time based on a simulation elapsed time required for executing the loop instruction sequence once, and
- wherein, when the loop instruction sequence detection signal is generated,
- the instruction executing section executes the loop instruction sequence once, and
- the elapsed time controller generates a simulation elapsed time required for executing the loop instruction sequence a predetermined number of times according to the loop instruction sequence elapsed time.
A simulation method performed by a simulation apparatus which comprises a CPU model including a loop instruction sequence pattern storage and a loop instruction sequence elapsed time storage, the simulation method causing the CPU model to:
- decode an instruction included in a program to be simulated and to generate a decode result;
- store a loop instruction sequence pattern defining a loop instruction sequence to be repeatedly executed in the loop instruction sequence pattern storage;
- sequentially compare an instruction included in the program to be simulated with the loop instruction sequence pattern and to generate a loop instruction sequence detection signal indicating that a plurality of instructions included in the program to be simulated matches the loop instruction sequence pattern;
- execute an instruction included in the program to be simulated according to the decode result;
- output a simulation elapsed time for which an instruction included in the program to be simulated is executed;
- store a loop instruction sequence elapsed time based on a simulation elapsed time required for executing the loop instruction sequence once in the loop instruction sequence elapsed time storage;
- and
- when the loop instruction sequence detection signal is generated, execute the loop instruction sequence once and to output a simulation elapsed time required for executing the loop instruction sequence a predetermined number of times according to the loop instruction sequence elapsed time.
A non-transitory computer readable medium storing a program for causing a simulation apparatus, which comprises a CPU model including a loop instruction sequence pattern storage and a loop instruction sequence elapsed time storage, to perform a simulation method, the simulation method causing the CPU model to:
- decode an instruction included in a program to be simulated and to generate a decode result;
- store a loop instruction sequence pattern defining a loop instruction sequence to be repeatedly executed in the loop instruction sequence pattern storage;
- sequentially compare an instruction included in the program to be simulated with the loop instruction sequence pattern and to generate a loop instruction sequence detection signal indicating that a plurality of instructions included in the program to be simulated matches the loop instruction sequence pattern;
- execute an instruction included in the program to be simulated according to the decode result;
- output a simulation elapsed time for which an instruction included in the program to be simulated is executed;
- store a loop instruction sequence elapsed time based on a simulation elapsed time required for executing the loop instruction sequence once in the loop instruction sequence elapsed time storage;
- and
- when the loop instruction sequence detection signal is generated, execute the loop instruction sequence once and to output a simulation elapsed time required for executing the loop instruction sequence a predetermined number of times according to the loop instruction sequence elapsed time.
Dependencies are inferred from the claim text.