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US 12,724,449 B2Granted
Asynchronous ASIC
AssigneeMagic Leap, Inc.
InventorsNiv Margalit, Eyal Sela
Life of this patent
Estimating the term…
Abstract
An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.
Claims20
An electronic device comprising:
- circuitry configured to:
- receive a first clock, the first clock configured to operate at a frequency;
- and
- receive a second clock and a third clock, wherein:
- the second clock is configured to operate at the frequency of the first clock and further configured to operate with a first phase shift with respect to the first clock,
- the third clock is configured to operate at the frequency of the first clock and further configured to operate with a second phase shift with respect to the first clock, and
- each of the second clock and the third clock is associated with a respective clock candidate selected from a plurality of clock candidates;
- wherein:
- each clock candidate of the plurality of clock candidates is associated with a respective phase shift relative to the first clock;
- the selecting the respective clock candidate associated with the second clock from the plurality of clock candidates comprises comparing, for a first data bit of a plurality of data bits, a first respective phase shift to a transition edge of the first clock;
- and
- the selecting the respective clock candidate associated with the third clock from the plurality of clock candidates comprises comparing, for a second data bit of the plurality of data bits, a second respective phase shift to a transition edge of the first clock.
9 more elements
A method, comprising:
- receiving, at an electronic device, a first clock, the first clock operating at a frequency;
- and
- receiving, at the electronic device, a second clock and a third clock, wherein:
- the second clock operates at the frequency of the first clock and operates with a first phase shift with respect to the first clock,
- the third clock operates at the frequency of the first clock and operates with a second phase shift with respect to the first clock, and
- each of the second clock and third clock is associated with a respective clock candidate selected from a plurality of clock candidates;
- wherein:
- each clock candidate of the plurality of clock candidates is associated with a respective phase shift relative to the first clock;
- the selecting the respective clock candidate associated with the second clock from the plurality of clock candidates comprises comparing, for a first data bit of a plurality of data bits, a first respective phase shift to a transition edge of the first clock;
- and
- the selecting the respective clock candidate associated with the third clock from the plurality of clock candidates comprises comparing, for a second data bit of the plurality of data bits, a second respective phase shift to a transition edge of the first clock.
8 more elements
A non-transitory computer-readable medium storing instructions which, when executed by one or more processors, cause the one or more processors to perform a method comprising:
- receiving, at an electronic device, a first clock, the first clock operating at a frequency;
- and
- receiving, at the electronic device, a second clock and a third clock, wherein:
- the second clock operates at the frequency of the first clock and operates with a first phase shift with respect to the first clock,
- the third clock operates at the frequency of the first clock and operates with a second phase shift with respect to the first clock, and
- each of the second clock and the third clock is associated with a respective clock candidate selected from a plurality of clock candidates;
- wherein:
- each clock candidate of the plurality of clock candidates is associated with a respective phase shift relative to the first clock;
- the selecting the respective clock candidate associated with the second clock from the plurality of clock candidates comprises comparing, for a first data bit of a plurality of data bits, a first respective phase shift to a transition edge of the first clock;
- and
- the selecting the respective clock candidate associated with the third clock from the plurality of clock candidates comprises comparing, for a second data bit of the plurality of data bits, a second respective phase shift to a transition edge of the first clock.
8 more elements
Dependencies are inferred from the claim text.