US 12,724,448 B2Granted

Semiconductor device, interface device and operation method

AssigneesGlobal Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.

InventorsBi-Yang Li, Igor Elkanovich, Hung-Yi Chang, Shih-Cheng Kao

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Abstract

An interface device is adapted for a semiconductor device including a first die and a second die. The first die and the second die are electrically connected to each other to be stacked into a 3D structure. The interface device includes a controllable delay line, a clock generator, and a phase detector (PD) arranged on the second die. The controllable delay line receives a source clock signal of the first die. The controllable delay line delays the source clock signal to generate a first delayed clock signal. The clock generator generates a second delayed clock signal according to the first delayed clock signal. The PD detects a phase difference between a gained clock signal of the first die and the second delayed clock signal to generate phase relationship information. Based on the phase relationship information, the controllable delay line adjusts a delay amount to the source clock signal.

Claims42

Dependent claims

An interface device adapted for a semiconductor device, wherein the semiconductor device comprises a first die and a second die, the first die and the second die are electrically connected to be stacked into a 3D structure, and the interface device comprises:

a controllable delay line arranged on the second die, wherein the controllable delay line receives a first source clock signal from the first die, and the controllable delay line adjusts a first delay amount to the first source clock signal according to an adjustment signal, thereby delaying the first source clock signal to generate a first delayed clock signal;
a clock generator arranged on the second die, wherein the clock generator is coupled to the controllable delay line to receive the first delayed clock signal, and the clock generator generates a second delayed clock signal according to the first delayed clock signal;
and
a phase detector arranged on the second die, wherein the phase detector receives a first gained clock signal from the first die, the phase detector is coupled to the clock generator to receive the second delayed clock signal, and the phase detector detects a phase difference between the first gained clock signal and the second delayed clock signal to generate phase relationship information,
wherein the adjustment signal is generated according to the phase relationship information.

2 more elements

An operation method of an interface device, wherein the interface device is adapted for a semiconductor device, the semiconductor device comprises a first die and a second die, the first die and the second die are electrically connected to be stacked into a 3D structure, and the operation method comprises:

receiving a first source clock signal from the first die by a controllable delay line of the interface device, wherein the controllable delay line is arranged on the second die;
adjusting a first delay amount to the first source clock signal according to an adjustment signal, thereby delaying the first source clock signal to generate a first delayed clock signal by the controllable delay line;
generating a second delayed clock signal according to the first delayed clock signal by a clock generator of the interface device, wherein the clock generator is arranged on the second die, and the clock generator is coupled to the controllable delay line to receive the first delayed clock signal;
receiving a first gained clock signal from the first die by a phase detector of the interface device, wherein the phase detector is arranged on the second die, and the phase detector is coupled to the clock generator to receive the second delayed clock signal;
detecting, by the phase detector, a phase difference between the first gained clock signal and the second delayed clock signal to generate phase relationship information;
and
generating the adjustment signal according to the phase relationship information.

4 more elements

A semiconductor device, wherein the semiconductor device comprises a first die and a second die, the first die and the second die are electrically connected to be stacked into a 3D structure, and the semiconductor device comprises:

a first clock transmission circuit arranged on the first die, wherein the first clock transmission circuit receives a first source clock signal of the first die, and the first clock transmission circuit generates a first gained clock signal based on the first source clock signal;
a first controllable delay line arranged on the second die, wherein the first controllable delay line receives the first source clock signal from the first die, and the first controllable delay line adjusts a first delay amount to the first source clock signal according to a first adjustment signal, thereby delaying the first source clock signal to generate a first delayed clock signal;
a first clock generator arranged on the second die, wherein the first clock generator is coupled to the first controllable delay line to receive the first delayed clock signal, and the first clock generator generates a second delayed clock signal according to the first delayed clock signal;
and
a first phase detector arranged on the second die, wherein the first phase detector receives the first gained clock signal from the first die, the first phase detector is coupled to the first clock generator to receive the second delayed clock signal, and the first phase detector detects a phase difference between the first gained clock signal and the second delayed clock signal to generate first phase relationship information,
wherein the first adjustment signal is generated according to the first phase relationship information.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/764,161Filed 4 Jul 2024
Published: US 2026/0010193 A18 Jan 2026
Granted: 1 Sep 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G06F 1/10
Generating or distributing clock signals or signals derived directly therefrom: distribution of clock signals , e.g. skew
H03K 5/14
Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals: by the use of delay lines
H04L 7/0008
Arrangements for synchronising receiver with transmitter: synchronisation information channels, e.g. clock distribution lines
H04L 7/0037
Correction by delay: delay of clock signal