LDO regulator circuit apparatus capable of attenuating supply voltage noise

An LDO regulator circuit apparatus capable of attenuating supply voltage noise comprising:

• a flipped voltage follower (FVF) regulator circuit unit having a pass transistor MPASS configured to adjust a supply voltage to output an output voltage;
• an error amplifying circuit unit configured to receive and compare a reference signal (VREF) and a feedback voltage (VOUT_DIV), wherein the feedback voltage is fed back from the output voltage through a feedback loop;
• a common gate (CG) circuit unit configured to amplify a feedback loop gain of the flipped voltage follower (FVF) regulator circuit unit;
• a super source follower circuit unit configured to buffer an output of the CG circuit unit and transmit it to a gate node of the pass transistor (MPASS);
• and
• a control circuit unit configured to transmit an output of the error amplifying circuit unit to a gate node of a transistor MCTRL according to a bias voltage,
• wherein the flipped voltage follower (FVF) regulator circuit unit comprises
• the transistor MCTRL Whose gate node is an input terminal of the flipped voltage follower (FVF) regulator circuit unit;
• and
• a transistor MBIAS operating as a current source,
• wherein a drain node of the pass transistor MPASS is connected to a source node of a transistor MCTRL, a drain node of the transistor MCTRL is connected to a drain node of a transistor MBIAS, and a source node of the transistor MBIAS is connected to ground,
• wherein the control circuit unit has a transistor MN1 and a transistor MP1,
• wherein a bias voltage (VB1) is applied to a source node of the transistor MP1, and a gate node of the transistor MP1 is connected to the gate node of the transistor MCTRL,
• wherein a gate node of the transistor MN1 receives an output signal of the error amplifying circuit unit, the source node is connected to the ground, and the drain node is connected to a drain node of the transistor MP1.