System on chip, bus power gating method thereof, and bus power gating system
AssigneeSamsung Electronics Co., Ltd.
InventorsIksu Lee, Jongsung Kang, Junghun Heo
Life of this patent
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Abstract
A power gating method of a system on chip includes transferring a first control signal to a bus by using a power management unit (PMU), transferring a response signal to the PMU by using the bus, in response to the first control signal, moving a transaction to a light bus circuit by using the bus, and transferring a second control signal to a power control circuit by using the PMU to adjust power supplied to the bus, based on the response signal.
Claims20
A power gating method of a system on chip including a power management unit (PMU) including at least one register, a power control circuit, and a bus including a main bus circuit, a light bus circuit, and a bus controller including processing circuitry configured to process a pending transaction that has not yet been processed and is pending at the bus, the power gating method comprising:
- transferring a first control signal from the PMU to the bus;
- transferring, in response to the first control signal, a response signal to the PMU prior to completion of the pending transaction;
- moving, by the bus controller, the pending transaction pending i) either at a combination of the main bus circuit and the light bus circuit or ii) exclusively at the main bus circuit to the light bus circuit after transferring the response signal from the bus to the PMU such that the pending transaction is moved internally within the bus to the light bus circuit subsequent to the pending transaction being received by the bus;
- and
- transferring a second control signal to the power control circuit by using the PMU to adjust power supplied to the bus, based on the response signal.
A system on chip comprising:
- a bus including a main bus circuit, a light bus circuit and a bus controller including processing circuitry, the bus being configured to process a pending transaction that has not yet been processed and is at the bus by using one or more of the main bus circuit and the light bus circuit and allow the pending transaction to be processed by the light bus circuit based on a transaction threshold value of the light bus circuit, the pending transaction being one of a plurality of transactions that has not yet been processed and is at the bus;
- a power control circuit including a main bus power switch, a light bus power switch, and a power path controller, the power control circuit being configured to control power supplied to the bus;
- and
- a power management unit (PMU) including at least one register, the PMU configured to,
- generate a first control signal and a second control signal based on an amount of the plurality of transactions,
- transfer the first control signal to the bus to control an operation of the bus, wherein, in response to the first control signal, the bus is configured to transfer a response signal to the PMU prior to the bus controller moving the pending transaction that is pending i) either at a combination of the main bus circuit and the light bus circuit or ii) exclusively at the main bus circuit to the light bus circuit after transferring the response signal to the PMU such that the pending transaction is moved internally within the bus to the light bus circuit subsequent to the pending transaction being received by the bus, and
- transfer the second control signal to the power control circuit to control an operation of the power control circuit.
A bus comprising:
- a main bus circuit, a light bus circuit and a bus controller including processing circuitry, the main bus circuit and the light bus circuit each configured to process a pending transaction, the pending transaction being one of the plurality of pending transactions of the bus that has not yet been processed, wherein,
- in response to an amount of the plurality of pending transactions being greater than or equal to a transaction threshold value of the light bus circuit, the bus is configured to process the pending transaction by using the main bus circuit and the light bus circuit, and
- in response to the amount of the plurality of pending transactions being less than the transaction threshold value, the bus is configured to process the pending transaction by using the light bus circuit by,
- transferring, in response to a first control signal from a power management unit (PMU), a response signal to the PMU prior to completion of the pending transaction on the bus, the PMU including at least one register, and
- moving, by the bus controller, the pending transaction that is pending i) either at a combination of the main bus circuit and the light bus circuit or ii) exclusively at the main bus circuit to the light bus circuit after transferring the response signal such that the pending transaction is moved internally within the bus to the light bus circuit subsequent to the pending transaction being received by the bus.
Dependencies are inferred from the claim text.