Semiconductor test apparatus and power supply method thereof

A semiconductor test apparatus comprising:

• a tester circuit including a power supply configured to simultaneously supply power to a plurality of devices under test (DUTs) during a test, a test signal transmitter configured to input a test signal to the plurality of DUTs and receive a response signal from the plurality of DUTs, a logic generation determiner circuit configured to generate the test signal and determine a failure of the plurality of DUTs, based on the response signal, and a controller configured to control the power supply and the logic generation determiner circuit;
• and
• a test board arranged between the tester circuit and the plurality of DUTs, the test board routing the power of the power supply and the test signal of the test signal transmitter to the plurality of DUTs, and routing the response signal from the plurality of DUTs to the test signal transmitter,
• wherein the power supply includes a plurality of power channels,
• the plurality of power channels are divided into a plurality of groups,
• each of the plurality of groups includes a set number of power channels, and
• each of the plurality of DUTs receives two or more types of power from the power channels, each type of power being power supplied at a respective supply voltage for a DUT,
• each of the plurality of groups shares a current output between the plurality of power channels and supplies the current output to each of the plurality of DUTs.

A semiconductor test apparatus comprising:

• a power supply configured to simultaneously supply power to a plurality of devices under test (DUTs) during a test;
• a test signal transmitter configured to input a test signal to the plurality of DUTs and receive a response signal from the plurality of DUTs;
• a logic generation determiner circuit configured to generate the test signal and determine a failure of the plurality of DUTs, based on the response signal;
• and
• a controller configured to control the power supply and the logic generation determiner circuit,
• wherein the power supply includes a plurality of power channels,
• the plurality of power channels are divided into a plurality of groups,
• each of the plurality of groups includes a set number of power channels, and
• each of the plurality of DUTs receives two or more types of power, each type of power being power supplied at a respective supply voltage for a DUT, each of the plurality of groups shares a current output between the plurality of power channels and supplies the shared current output to each of the plurality of DUTs.