Wafer-scale integration with a stiffening isometric grid array

An apparatus for stiffening comprising:

• a wafer-scale silicon interposer (WSSI), wherein a front side of the WSSI is bonded to a plurality of functional chips, and wherein the WSSI includes a plurality of through-silicon vias (TSVs);
• an isometric grid array (IGA), wherein a back side of the WSSI is inserted into the IGA, wherein the IGA stiffens the WSSI, and wherein the back side of the WSSI remains accessible via a plurality of open recesses within the IGA;
• a plurality of modular power substrates (MPSs), wherein the plurality of MPSs is attached to the back side of the WSSI through the plurality of open recesses;
• and
• a unified circuit board (UCB), wherein the UCB is mechanically connected to the plurality of MPSs, wherein the UCB includes a plurality of DC-to-DC converters, and wherein the UCB sends DC power to the plurality of functional chips bonded to the WSSI, wherein the sending is based on the plurality of MPSs and the plurality of TSVs.

A system for stiffening comprising:

• a wafer-scale silicon interposer (WSSI), wherein a front side of the WSSI is bonded to a plurality of functional chips, and wherein the WSSI includes a plurality of through-silicon vias (TSVs);
• an isometric grid array (IGA), wherein a back side of the WSSI is inserted into the IGA, wherein the IGA stiffens the WSSI, and wherein the back side of the WSSI remains accessible via a plurality of open recesses within the IGA;
• a plurality of modular power substrates (MPSs), wherein the plurality of MPSs is attached to the back side of the WSSI through the plurality of open recesses;
• and
• a unified circuit board (UCB), wherein the UCB is connected mechanically to the plurality of MPSs, wherein the UCB includes a plurality of DC-to-DC converters, wherein the system, when provided DC power, is configured to:
• send DC power to the plurality of functional chips bonded to the WSSI that was stiffened, wherein the sending is based on the plurality of DC-to-DC converters, the plurality of MPSs, and the plurality of TSVs.