Memory chip, logic chip, chip-stacked structure, and memory
AssigneeCXMT Corporation
InventorJiarui Zhang
Life of this patent
Estimating the term…
Abstract
Provided are a memory chip, a logic chip, a chip-stacked structure, and a memory. A global signal region of the memory chip is penetrated by multiple conductive via groups, and each conductive via group includes a first dummy conductive via group and a second dummy conductive via group. The first dummy conductive via group includes a first conductive via and a fourth conductive via, and the second dummy conductive via group includes a second conductive via and a third conductive via. The first dummy conductive via group is configured to transmit the same first global signal, and the second dummy conductive via group is configured to transmit the same second global signal.
Claims20
A memory chip, a center point of an active surface of the memory chip and an adjacent region of the center point being defined as a global signal region, and a center point of the global signal region coinciding with the center point of the active surface;
- the global signal region being penetrated by a plurality of conductive via groups, each conductive via group comprising a first dummy conductive via group and a second dummy conductive via group, the first dummy conductive via group comprising a first conductive via and a fourth conductive via, and the second dummy conductive via group comprising a second conductive via and a third conductive via;
- and the first dummy conductive via group being configured to transmit a same first global signal, and the second dummy conductive via group being configured to transmit a same second global signal;
- and
- for each conductive via group, the first conductive via and the second conductive via being symmetric about a first axis, the third conductive via and the fourth conductive via being symmetric about the first axis, and the first conductive via and the fourth conductive via being symmetric about a second axis;
- and the first axis and the second axis being perpendicular to each other and intersecting at the center point of the active surface, the first axis being parallel to a first side edge of the memory chip, and the second axis being parallel to a second side edge of the memory chip.
A logic chip, a center point of an active surface of the logic chip and an adjacent region of the center point being defined as a global signal region, and a center point of the global signal region coinciding with the center point of the active surface;
- the global signal region being penetrated by a plurality of conductive via groups, each conductive via group comprising a first dummy conductive via group and a second dummy conductive via group, the first dummy conductive via group comprising a first conductive via and a fourth conductive via, and the second dummy conductive via group comprising a second conductive via and a third conductive via;
- and the first dummy conductive via group being configured to transmit a same first global signal, and the second dummy conductive via group being configured to transmit a same second global signal;
- and
- for each conductive via group, the first conductive via and the second conductive via being symmetric about a first axis, the third conductive via and the fourth conductive via being symmetric about the first axis, and the first conductive via and the fourth conductive via being symmetric about a second axis;
- and the first axis and the second axis being perpendicular to each other and intersecting at the center point of the active surface, the first axis being parallel to a first side edge of the logic chip, and the second axis being parallel to a second side edge of the logic chip.
Dependencies are inferred from the claim text.