Semiconductor package including a plurality of semiconductor chips in a stacked structure

A semiconductor package, comprising:

• a first semiconductor chip;
• a second semiconductor chip stacked on the first semiconductor chip;
• and
• a plurality of external connection terminals electrically coupled to a lower surface of the first semiconductor chip,
• wherein the first semiconductor chip comprises:
• a substrate comprising the lower surface and an upper surface opposite to the lower surface;
• a lower wiring layer in a lower portion of the lower surface comprising a first plurality of wiring patterns;
• an upper wiring layer in an upper portion of the upper surface and comprising a second plurality of wiring patterns;
• a plurality of through structures electrically coupling the lower wiring layer to the upper wiring layer and penetrating the substrate;
• and
• a macro cell disposed between the plurality of through structures,
• wherein the second plurality of wiring patterns extends in a first horizontal direction,
• wherein wiring patterns of the second plurality of wiring patterns are spaced apart from each other by a first pitch distance in a second horizontal direction, and
• wherein at least one through structure of the plurality of through structures at least partially overlaps a wiring pattern of the upper wiring layer in a vertical direction within an overlapping distance from the wiring pattern of the upper wiring layer, the overlapping distance being half of the first pitch distance.

A semiconductor package, comprising:

• a first semiconductor chip;
• a second semiconductor chip stacked on the first semiconductor chip;
• and
• a plurality of external connection terminals electrically coupled to a lower surface of the first semiconductor chip,
• wherein the first semiconductor chip comprises a power delivery network (PDN) configured to deliver power signals to the second semiconductor chip via the plurality of external connection terminals,
• wherein the PDN of the first semiconductor chip comprises:
• a first wiring layer comprising a first plurality of wiring patterns;
• a second wiring layer comprising a second plurality of wiring patterns and formed at a second level different from a first level of the first wiring layer;
• and
• a plurality of through structures electrically coupling the first wiring layer to the second wiring layer,
• wherein the first plurality of wiring patterns extends in a first horizontal direction,
• wherein wiring patterns of the first plurality of wiring patterns are spaced apart from each other by a first pitch distance in a second horizontal direction, and
• wherein at least one through structure at least partially overlaps a wiring pattern of the first wiring layer in a vertical direction within an overlapping distance from the wiring pattern of the first wiring layer, the overlapping distance being half of the first pitch distance.