Semiconductor package and method of manufacturing the same

A semiconductor package comprising:

• a lower redistribution layer;
• a lower semiconductor chip including a first active surface with first connection pads thereon and a first inactive surface opposite the first active surface, the lower semiconductor chip on the lower redistribution layer such that the first active surface faces the lower redistribution layer, the first connection pads being connected to the lower redistribution layer;
• an upper semiconductor chip having an area larger than an area of the lower semiconductor chip and including a second active surface with second connection pads thereon and a second inactive surface opposite the second active surface, the upper semiconductor chip on the lower semiconductor chip such that the second active surface faces the lower semiconductor chip;
• an intermediate connection member including an upper redistribution layer on the second active surface of the upper semiconductor chip between the lower semiconductor chip and the upper semiconductor chip and connected to each of the second connection pads;
• a plurality of vertical interconnectors disposed around the lower semiconductor chip on the lower redistribution layer and connecting the lower redistribution layer and the upper redistribution layer to each other;
• and
• a molding layer on the lower redistribution layer surrounding the lower semiconductor chip and the plurality of vertical interconnectors and extending upwardly along side surfaces of the upper semiconductor chip and the intermediate connection member, the molding layer including an upper surface that is substantially coplanar with the second inactive surface of the upper semiconductor chip,
• wherein the lower redistribution layer has an area larger than an area of the intermediate connection member,
• wherein the lower redistribution layer includes an outside surface that is substantially coplanar with an outside surface of the molding layer, and
• wherein the outside surface of the molding layer is exposed to the outside.

A semiconductor package comprising:

• a first semiconductor chip including a first surface with first connection pads thereon and a second surface opposite the first surface;
• a first connection member on the first surface of the first semiconductor chip and including a first redistribution layer electrically connected to the first connection pads, the first connection member having the same planar area as the first semiconductor chip;
• a second semiconductor chip including a first surface with second connection pads thereon and a second surface opposite the first surface and bonded to one region of the first connection member;
• a second redistribution layer on the first surface of the second semiconductor chip electrically connected to the second connection pads, the second redistribution layer having a planar area larger than a planar area of the first semiconductor chip;
• a plurality of vertical interconnectors disposed around the second semiconductor chip on the second redistribution layer and connecting the first redistribution layer and the second redistribution layer to each other;
• and
• a molding portion on the second redistribution layer surrounding the second semiconductor chip and the plurality of vertical interconnectors and extending upwardly on side surfaces of the first semiconductor chip and the first connection member,
• wherein the first connection member is between the first semiconductor chip and the second semiconductor chip,
• wherein the second redistribution layer has an area larger than an area of the first connection member,
• wherein the semiconductor package further includes a bonding layer between the second surface of the second semiconductor chip and the first connection member,
• wherein the bonding layer contacts each of the second surface of the second semiconductor chip and the first connection member,
• wherein the molding portion includes an extended portion covering the first surface of the second semiconductor chip,
• the semiconductor package further comprises a plurality of conductive posts respectively disposed on the second connection pads and penetrating through the extended portion of the molding portion, and the second redistribution layer is connected to the plurality of conductive posts, and
• wherein an entire length of each of the plurality of conductive posts extending between the second connection pad and the second redistribution layer is in direct contact with the extended portion of the molding portion.